Rainbow Electronics ATF1502ASV - Manual (Page 3)

3
ATF1502ASV
1615G–PLD–09/02
Block Diagram
Each of the 32 macrocells generates a buried feedback that goes to the global bus.
Each input and I/O pin also feeds into the global bus. The switch matrix in each logic
block then selects 40 individual signals from the global bus. Each macrocell also gener-
ates a foldback logic term that goes to a regional bus. Cascade logic between
macrocells in the ATF1502ASV allows fast, efficient generation of complex logic func-
tions. The ATF1502ASV contains four such logic chains, each capable of creating sum
term logic with a fan-in of up to 40 product terms.
The ATF1502ASV macrocell, shown in Figure 1, is flexible enough to support highly
complex logic functions operating at high speed. The macrocell consists of five sections:
product terms and product term select multiplexer, OR/XOR/CASCADE logic, a flip-flop,
output select and enable, and logic array inputs.
Unused product terms are automatically disabled by the compiler to decrease power
consumption. A security fuse, when programmed, protects the contents of the
ATF1502ASV. Two bytes (16 bits) of User Signature are accessible to the user for pur-
poses such as storing project name, part number, revision or date. The User Signature
is accessible regardless of the state of the security fuse.
The ATF1502ASV device is an in-system programmable (ISP) device. It uses the indus-
try standard 4-pin JTAG interface (IEEE Std. 1149.1), and is fully compliant with JTAG’s
B
32