Rainbow Electronics ATF1502ASV - Manual (Page 8)

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ATF1502ASV
1615G–PLD–09/02
When using the ISP hardware or software to program the ATF1502ASV devices, four
I/O pins must be reserved for the JTAG interface. However, the logic features that the
macrocells have associated with these I/O pins are still available to the design for
burned logic functions.
To facilitate ISP programming by the Automated Test Equipment (ATE) vendors. Serial
Vector Format (SVF) files can be created by Atmel-provided software utilities.
ATF1502ASV devices can also be programmed using standard third-party program-
mers. With a third-party programmer, the JTAG ISP port can be disabled, thereby
allowing four additional I/O pins to be used for logic.
Contact your local Atmel representatives or Atmel PLD applications for details.
ISP Programming
Protection
The ATF1502ASV has a special feature that locks the device and prevents the inputs
and I/O from driving if the programming process is interrupted for any reason. The
inputs and I/O default to high-Z state during such a condition. In addition, the pin-keeper
option preserves the previous state of the input and I/O PMS during programming.
All ATF1502ASV devices are initially shipped in the erased state, thereby making them
ready to use for ISP.
Note: For more information refer to the “Designing for In-System Programmability with Atmel
CPLDs” application note.
JTAG-BST/ISP
Overview
The JTAG boundary-scan testing is controlled by the Test Access Port (TAP) controller
in the ATF1502ASV. The boundary-scan technique involves the inclusion of a shift-reg-
ister stage (contained in a boundary-scan cell) adjacent to each component so that
signals at component boundaries can be controlled and observed using scan testing
methods. Each input pin and I/O pin has its own boundary-scan cell (BSC) to support
boundary-scan testing. The ATF1502ASV does not include a Test Reset (TRST) input
pin because the TAP controller is automatically reset at power-up. The five JTAG modes
supported include: SAMPLE/PRELOAD, EXTEST, BYPASS, IDCODE and HIGHZ. The
ATF1502ASV’s ISP can be fully described using JTAG’s BSDL as described in IEEE
Standard 1149.1b. This allows ATF1502ASV programming to be described and imple-
mented using any one of the third-party development tools supporting this standard.
The ATF1502ASV has the option of using four JTAG-standard I/O pins for boundary-
scan testing (BST) and in-system programming (ISP) purposes. The ATF1502ASV is
programmable through the four JTAG pins using the IEEE standard JTAG programming
protocol established by IEEE Standard 1149.1 using 5V TTL-level programming signals
from the ISP interface for in-system programming. The JTAG feature is a programmable
option. If JTAG (BST or ISP) is not needed, then the four JTAG control pins are avail-
able as I/O pins.
JTAG Boundary-scan
Cell (BSC) Testing
The ATF1502ASV contains up to 32 I/O pins and four input pins, depending on the
device type and package type selected. Each input pin and I/O pin has its own bound-
ary-scan cell (BSC) in order to support boundary-scan testing as described in detail by
IEEE Standard 1149.1. A typical BSC consists of three capture registers or scan regis-
ters and up to two update registers. There are two types of BSCs, one for input or I/O
pin, and one for the macrocells. The BSCs in the device are chained together through
the capture registers. Input to the capture register chain is fed in from the TDI pin while
the output is directed to the TDO pin. Capture registers are used to capture active
device data signals, to shift data in and out of the device and to load data into the update
registers. Control signals are generated internally by the JTAG TAP controller. The BSC
configuration for the input and I/O pins and macrocells is shown below.