Rainbow Electronics AT75C310 - Manual (Page 15)

AT75C310
15
EBI: External Bus Interface
The EBI generates the signals which control access to the
external memory or peripheral devices. The EBI is fully pro-
grammable and can address up to 64 megabytes. Its main
characteristic is to allow the connection of both static and
dynamic memories on the same bus. The address and data
lines are shared between static and dynamic devices
whereas the control lines are distinct. The control lines are
driven by two separate subsystems: the SMC (static mem-
ory controller) and the DMC (dynamic memory controller).
The static devices include regular static memories and
memory-mapped peripherals. The supported dynamic
devices are mainly EDO RAMs.
SMC: Static Memory Controller
The static memory controller (SMC) is used by the
AT75C310 to access external static memory devices.
Static memory devices include external Flash, SRAM or
peripherals.
The SMC provides a glueless memory interface to external
memory using the common address and data bus and
some dedicated control signals. The SMC is highly pro-
grammable and has up to 24 bits of address bus, a 32- or
16-bit data bus and up to four chip select lines. The SMC
supports different access protocols allowing single clock-
cycle accesses. The SMC is programmed as an internal
peripheral that has a standard APB bus interface and a set
of memory-mapped registers. The SMC shares the exter-
nal address and data buses with the DMC and any external
bus master.
External Memory Mapping
The memory map associates the internal 32-bit address
space with the external 24-bit address bus. The memory
map is defined by programming the base address and
page size of the external memories. Note that A2 - A23 is
only significant for 32-bit memory and A1 - A23 for 16-bit
memory.
If the physical memory-mapped device is smaller than the
programmed page size, it wraps around and appears to be
repeated within the page. The SMC correctly handles any
valid access to the memory device within the page.
In the event of an access request to an address outside
any programmed page, an abort signal is generated by the
internal decoder. Two types of abort are possible: instruc-
tion prefetch abort and data abort. The corresponding
e x c e p t i o n v e c t o r a d d re s s e s a r e 0 x0 0 0 0 0 0 0 C a n d
0x00000010. It is up to the system programmer to program
the exception handling routine used in case of an abort.
If the AT75C310 is in internal boot mode, any chip select
configured with a base address of zero will be disabled as
the internal ROM is mapped to address zero.