Rainbow Electronics AT75C310 - Manual (Page 32)

AT75C310
32
code then checks the interrupt number and
branches to the required service routine.
6. The service routine should start by saving the Link
Register (R14_irq) and the SPSR (SPSR_irq). Note
that the Link Register must be decremented by four
when it is saved if it is to be restored directly into the
Program Counter at the end of the interrupt. Alter-
natively, this can be done at the start of the default
handler.
7. Further interrupts can then be unmasked by clear-
ing the “I” bit in the CPSR, allowing re-assertion of
the NIRQ to be taken into account by the core. This
occurs if an interrupt with a higher priority than the
current one occurs.
8. The Interrupt Handler then proceeds as required,
saving the registers which will be used and restor-
ing them at the end. During this phase, an interrupt
of priority higher than the current level restarts the
sequence from step 1. Note that if the interrupt is
programmed to be level sensitive, the source of the
interrupt must be cleared during this phase.
9. The “I” bit in the CPSR must be set in order to mask
interrupts before exiting to ensure that the interrupt
is completed in an orderly manner.
10. The service routine should then branch to the com-
mon exit routine.
11. The stored priority level is fetched (from a stack)
and witten to the End Of Interrupt Command Regis-
ter (AIC_EOICR) in order to indicate to the AIC that
the current interrupt is finished. This restores the
previous current level if one existed. If another inter-
rupt is pending with lower or equal priority than the
old current level but with higher priority than the new
current level, the NIRQ line is re-asserted. The
interrupt sequence does not immediately start
because the “I” bit is set in the core.
12. The SPSR (SPSR_irq) is restored. Finally, the
saved value of the Link Register is restored directly
into the PC. This has the effect of returning from the
interrupt to whatever was being executed before
and of loading the CPSR with the stored SPSR,
masking or unmasking the interrupts depending on
the state saved in the SPSR (the previous state of
the ARM core).
Note that the “I” bit in the SPSR is significant. If it is set, it
indicates that the ARM core was just about to mask IRQ
interrupts when the mask instruction was interrupted.
Hence, when the SPSR is restored, the mask instruction is
completed (IRQ is masked).
Fast Interrupt Sequence
It is assumed that:
• The AIC has been programmed and the fast interrupt is
enabled.
• The instruction at address 0x1C (FIQ exception vector
address) is a branch to an FIQ service routine or the first
instruction of the FIQ routine
Nested fast interrupts are not needed by the user.
When NFIQ is asserted, if the bit “F” of CPSR is 0, the
sequence is:
1. The CPSR is stored in SPSR_fiq, the current value
of the Program Counter is loaded in the FIQ link
register (R14_fiq) and the Program Counter (R15) is
loaded with 0x1C. In the following cycle, during
fetch at address 0x20, the ARM core adjusts
R14_fiq, decrementing it by four.
2. The ARM core enters FIQ mode and starts execut-
ing the instruction at address 0x1c, which may be a
branch or the first service routine instruction.
3. The AIC_FVR register is read. This results in the
cancellation of the FIQ request and returns 0x0.
4. The previous step has the effect of branching to the
corresponding interrupt service routine. It is not
necessary to save the Link Register (R14_fiq) and
the SPSR (SPSR_fiq) if nested fast interrupts are
not needed.
5. The Interrupt Handler then proceeds as required. It
is not necessary to save registers R8 to R13
because FIQ mode has its own dedicated registers
and the user R8 to R13 are banked. The other reg-
isters, R0 to R7, must be saved before being used,
and restored at the end (before the next step). Note
that if the fast interrupt is programmed to be level
sensitive, the source of the interrupt must be
cleared during this phase in order to de-assert the
NFIQ line.
6. Finally, the Link Register (R14_fiq) is restored into
the PC after decrementing it by 4 (with instruction
sub pc, lr, #4 for example). This has the effect of
returning from the interrupt to whatever was being
executed before, and of loading the CPSR with the
SPSR, masking or unmasking the fast interrupt
depending on the state saved in the SPSR.
Note that the “F” bit in the SPSR is significant. If it is set, it
indicates that the ARM core was just about to mask FIQ
interrupts when the mask instruction was interrupted.
Hence, when the SPSR is restored, the interrupted instruc-
tion is completed (FIQ is masked).