Rainbow Electronics AT75C310 - Manual (Page 40)

AT75C310
40
PIO: Parallel I/O Controller
The AT75C310 has 23 programmable I/O lines. Three pins
on the AT75C310 are dedicated as general-purpose I/O
pins. Other I/O lines are multiplexed with an external signal
of a peripheral to optimize the use of available package
pins. Refer to Table 13 and Table 14 on page 42. These
lines are controlled by two separate and identical PIO con-
trollers, PIO A and PIO B. Each PIO controller also pro-
vides an internal interrupt signal to the AIC.
Multiplexed I/O Lines
Most I/O lines are multiplexed with an I/O signal of a
peripheral. After reset, the pin is controlled by the PIO con-
troller and is in input mode.
When a peripheral signal is not used in an application, the
corresponding pin can be used as a parallel I/O. Each par-
allel I/O line is bi-directional, whether the peripheral defines
the signal as input or output. Figure 8 shows the multiplex-
ing of the peripheral signals with parallel I/O signals.
If a pin is multiplexed between the PIO controller and a
peripheral, the pin is controlled by the registers PIO_PER
(PIO Enable) and PIO_PDR (PIO Disable). The register
PIO_PSR (PIO Status) indicates whether the pin is con-
trolled by the corresponding peripheral or by the PIO con-
troller.
If a pin is a general-purpose parallel I/O pin (not multi-
plexed with a peripheral), PIO_PER and PIO_PDR have no
effect and PIO_PSR returns 1 for the bits corresponding to
these pins.
When the PIO is selected, the peripheral input line is con-
nected to zero.
Output Selection
The user can enable each individual I/O signal as an output
w i t h t h e re g i s t e r s P I O _ O ER ( O u t p u t E n a b l e ) a n d
PIO_ODR (Output Disable). The output status of the I/O
signals can be read in the register PIO_OSR (Output Sta-
tus). The direction defined has an effect only if the pin is
configured to be controlled by the PIO controller.
I/O Levels
Each pin can be configured to be driven high or low. The
level is defined in four different ways, according to the fol-
lowing conditions:
1. If a pin is controlled by the PIO Controller and is
defined as an output (see “Output Selection”
above), the level is programmed using the registers
PIO_SODR (Set Output Data) and PIO_CODR
(Clear Output Data). In this case, the programmed
value can be read in PIO_ODSR (Output Data
Status).
2. If a pin is controlled by the PIO controller and is not
defined as an output, the level is determined by the
external circuit.
3. If a pin is not controlled by the PIO controller, the
state of the pin is defined by the peripheral.
4. In all cases, the level on the pin can be read in the
register PIO_PDSR (Pin Data Status).
Filters
Optional input glitch filtering is available on each pin and is
controlled by the registers PIO_IFER (Input Filter Enable)
and PIO_IFDR (Input Filter Disable). Input glitch filtering
can be selected whether the pin is used for its peripheral
function or as a parallel I/O line. The register PIO_IFSR
(Input Filter Status) indicates whether or not the filter is
activated for each pin.
Interrupts
Each parallel I/O can be programmed to generate an inter-
rupt when a level change occurs. This is controlled by the
PIO_IER (Interrupt Enable) and PIO_IDR (Interrupt Dis-
able) registers which enable/disable the I/O interrupt by
setting/clearing the corresponding bit in the PIO_IMR.
When a change in level occurs, the corresponding bit in the
PIO_ISR (Interrupt Status) is set whether the pin is used as
a PIO or a peripheral and whether it is defined as input or
output. If the corresponding interrupt in PIO_IMR (Interrupt
Mask) is enabled, the PIO interrupt is asserted.
When PIO_ISR is read, the register is automatically
cleared.
User Interface
Each individual I/O is associated with a bit position in the
Parallel I/O User Interface Registers. Each of these regis-
ters is 32 bits wide. If a parallel I/O line is not defined, writ-
ing to the corresponding bits has no effect. Undefined bits
read as zero.