Rainbow Electronics AT42QT1110-AZ - Manual (Page 32)

32
9570H–AT42–02/10
AT42QT1110-MZ/AT42QT1110-AZ
PHYST: positive hysteresis. This setting provides a greater degree of control over the
implementation of the positive threshold recalibration. The positive hysteresis operates as a
“modifier” for the positive threshold. When a key signal is detected as being over the positive
threshold, the positive threshold is reduced by a factor corresponding to the positive hysteresis
so that the key will not go in and out of positive detection when the signal is on the borderline
between drift-compensation of a positive error or recalibration.
The settings for positive hysteresis are:
00 = No change to positive threshold
01 = 12.5 percent reduction in positive-detect threshold
10 = 25% reduction in positive-detect threshold
11 = 37.5% reduction in positive-detect threshold
Default PTHR value: 4 (4 counts above reference)
Default PHYST value: 2 (25% positive hysteresis)
7.8 Address 4: Positive Drift Compensation (PDRIFT)
When changing ambient conditions cause a change in the key signal, the QT1110 will
compensate through its drift functions. “Positive Drift” refers to the case where the signal for a
key is greater than the reference.
Drift compensation occurs at a rate of 1 count per drift compensation period.
PDRIFT: the drift compensation period, in multiples of 160 ms. The valid range is 0 to 127,
where 0 disables positive drift compensation.
Note: Drift compensation timing is paused while Drift Hold is activated, and continued when
Drift Hold has timed out.
Default value: 6 (960 ms)
7.9 Address 5: Positive Recalibration Delay (PRD)
If a key signal is determined to be above the positive threshold, the QT1110 will wait for this
delay and confirm that the error condition is still present before initiating a recalibration.
PRD: the positive recalibration delay, in multiples of 160 ms.
Note: All keys are recalibrated in the case of a positive recalibration.
Default value: 6 (960 ms)
Table 7-7. Positive Drift Compensation
Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
4 0 PDRIFT
Table 7-8. Positive Recalibration Delay
Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
5 PRD