Rainbow Electronics DS1644P - Manual (Page 5)

DS1644/DS1644P
5 of 11
RETRIEVING DATA FROM RAM OR CLOCK
The DS1644 is in the read mode whenever WE (write enable) is high, and CE (chip enable) is low. The
device architecture allows ripple-through access to any of the address locations in the NV SRAM. Valid
data will be available at the DQ pins within t
AA
after the last address input is stable, providing that the CE
and OE access times and states are satisfied. If CE or OE access times are not met, valid data will be
available at the latter of chip enable access (t
CEA
) or at output enable access time (t
OEA
). The state of the
data input/output pins (DQ) is controlled by CE and OE . If the outputs are activated before t
AA
, the data
lines are driven to an intermediate state until t
AA
. If the address inputs are changed while CE and OE
remain valid, output data will remain valid for output data hold time (t
OH
) but will then go indeterminate
until the next address access.
WRITING DATA TO RAM OR CLOCK
The DS1644 is in the write mode whenever WE and CE are in their active state. The start of a write is
referenced to the latter occurring high to low transition of WE or CE . The addresses must be held valid
throughout the cycle. CE or WE must return inactive for a minimum of t
WR
prior to the initiation of
another read or write cycle. Data in must be valid t
DS
prior to the end of write and remain valid for t
DH
afterward. In a typical application, the OE signal will be high during a write cycle. However, OE can be
active provided that care is taken with the data bus to avoid bus contention. If OE is low prior to WE
transitioning low the data bus can become active with read data defined by the address inputs. A low
transition on WE will then disable the outputs t
WEZ
after WE goes active.
DATA RETENTION MODE
When V
CC
is within nominal limits (V
CC
> 4.5 volts) the DS1644 can be accessed as described above with
read or write cycles. However, when V
CC
is below the power-fail point V
PF
(point at which write
protection occurs) the internal clock registers and RAM are blocked from access. This is accomplished
internally by inhibiting access via the CE signal. At this time the power-fail output signal ( PFO ) will be
driven active low and will remain active until V
CC
returns to nominal levels. When V
CC
falls below the
level of the internal battery supply, power input is switched from the V
CC
pin to the internal battery and
clock activity, RAM, and clock data are maintained from the battery until V
CC
is returned to nominal
level.