Rainbow Electronics DS1554 - Manual (Page 6)

DS1554
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DS1554 REGISTER MAP Table 2
DATA
ADDRESS
B
7
B
6
B
5
B
4
B
3
B
2
B
1
B
0
FUNCTION/RANGE
7FFFh 10 Year YEAR YEAR 00-99
7FFEh X X X 10 M MONTH MONTH 01-12
7FFDh X X 10 Date DATE DATE 01-31
7FFCh X FT X X X DAY DAY 01-07
7FFBh X X 10 HOUR HOUR HOUR 00-23
7FFAh X 10 MINUTES MINUTES MINUTES 00-59
7FF9h OSC 10 SECONDS SECONDS SECONDS 00-59
7FF8h W R 10 CENTURY CENTURY CONTROL 00-39
7FF7h WDS BMB4 BMB3 BMB2 BMB1 BMB0 RB1 RB0 WATCHDOG
7FF6h AE Y ABE Y Y Y Y Y INTERRUPTS
7FF5h AM4 Y 10 DATE DATE ALARM DATE 01-31
7FF4h AM3 Y 10 HOURS HOURS ALARM HOURS 00-23
7FF3h AM2 10 MINUTES MINUTES ALARM MINUTES 00-59
7FF2h AM1 10 SECONDS SECONDS ALARM SECONDS 00-59
7FF1h Y Y Y Y Y Y Y Y UNUSED
7FF0h WF AF 0 BLF 0 0 0 0 FLAGS
X = Unused, read/writeable under Write and Read AE = Alarm Flag Enable
bit control Y = Unused, read/writeable without Write and Read
FT = Frequency Test bit bit control
OSC = Oscillator start/stop bit ABE = Alarm in battery Back-up mode enable
W = Write bit AM1-AM4 = Alarm Mask bits
R = Read bit WF = Watchdog Flag
WDS = Watchdog Steering bit AF = Alarm Flag
BMB0-BMB4 = Watchdog Multiplier bits 0 = 0 and are read only
RB0-RB1 = Watchdog Resolution bits BLF = Battery Low Flag
CLOCK OSCILLATOR CONTROL
The Clock oscillator may be stopped at any time. To increase the shelf life of the backup lithium battery
source, the oscillator can be turned off to minimize current drain from the battery. The
OSC bit is the
MSB of the Seconds Register (B7 of 7FF9h). Setting it to a 1 stops the oscillator, setting to a 0 starts the
oscillator. The DS1554 is shipped from Dallas Semiconductor with the clock oscillator turned off,
OSC
bit set to a 1.
READING THE CLOCK
When reading the RTC data, it is recommended to halt updates to the external set of double-buffered RTC
Registers. This puts the external registers into a static state allowing data to be read without register
values changing during the read process. Normal updates to the internal registers continue while in this
state. External updates are halted when a 1 is written into the read bit, B6 of the Control Register (7FF8h).
As long as a 1 remains in the Control Register read bit, updating is halted. After a halt is issued, the
registers reflect the RTC count (day, date, and time) that was current at the moment the halt command
was issued. Normal updates to the external set of registers will resume within 1 second after the read bit is
set to a 0 for a minimum of 500
µ
s. The read bit must be a zero for a minimum of 500
µ
s to ensure the
external registers will be updated.