Rainbow Electronics DS1631 - Manual (Page 7)

DS1631
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2-WIRE SERIAL DATA BUS
The DS1631 communicates over a standard bidirectional 2-wire serial data bus that consists of a serial
clock (SCL) signal and serial data (SDA) signal. The DS1631 interfaces to the bus through the SCL input
pin and open-drain SDA I/O pin.
The following terminology is used to describe 2-wire communication:
Master Device: Microprocessor/microcontroller that controls the slave devices on the bus. The master
device generates the SCL signal and START and STOP conditions.
Slave: All devices on the bus other than the master. The DS1631 always functions as a slave.
Bus Idle or Not Busy: Both SDA and SCL remain high. SDA is held high by a pullup resistor when the
bus is idle, and SCL must either be forced high by the master (if the SCL output is push-pull) or pulled
high by a pullup resistor (if the SCL output is open-drain).
Transmitter: A device (master or slave) that is sending data on the bus.
Receiver: A device (master or slave) that is receiving data from the bus.
START Condition: Indicates the beginning of a data transfer to all devices on the bus. The master
generates a START condition by pulling SDA from high to low while SCL is high (see Figure 5). A
repeated START is sometimes used at the end of a data transfer (instead of a STOP) to indicate that the
master will perform another operation.
STOP Condition: Indicates the end of a data transfer to all devices on the bus. The master generates a
STOP condition by transitioning SDA from low to high while SCL is high (see Figure 5). After the
STOP is issued, the master releases the bus to its idle state.
Acknowledge (ACK): When a device (either master or slave) is acting as a receiver, it must generate an
acknowledge (ACK) on the SDA line after receiving every byte of data. The receiving device performs an
ACK by pulling the SDA line low for an entire SCL period (see Figure 5). During the ACK clock cycle,
the transmitting device must release SDA. A variation on the ACK signal is the “not acknowledge”
(NACK). When the master device is acting as a receiver, it uses a NACK instead of an ACK after the last
data byte to indicate that it is finished receiving data. The master indicates a NACK by leaving the SDA
line high during the ACK clock cycle.
Slave Address: Every slave device on the bus must have a unique 7-bit address that allows the master to
access that device. The DS1631’s 7-bit bus address is as follows:
bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
1 0 0 1 A
2
A
1
A
0
where bits 2, 1, and 0 are user selectable through the A
2
, A
1
, and A
0
pins. The three user-selectable
address bits allow up to eight DS1631s to be multi-dropped on the same bus.
Control Byte: The control byte is transmitted by the master and consists of the 7-bit slave address plus a
read/write (R/
W ¯¯ ) bit. If the master is going to read data from the slave device then R/ W ¯¯ = 1, and if the
master is going to write data to the slave device then R/ W ¯¯ = 0.
Command Byte: The command byte can be any of the command protocols described in the DS1631
COMMAND SET section of this data sheet.