Rainbow Electronics DS1870 - Manual (Page 14)

DS1870
LDMOS RF Power-Amplifier Bias
Controller
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As the device powers up, the V CC LO alarm flag
defaults to a 1 until the first V CC ADC conversion
occurs and sets or clears the flag accordingly. The
FAULT output is active when V
CC < V POA .
Memory Description
The DS1870 memory map is divided into six sections
that include the lower memory (addresses 00h to 7Fh)
and five memory tables (Figure 2). The memory tables
are addressed by setting the table-select byte (7Fh) to
the desired table number and accessing the upper
memory locations (80h to FFh). The lower memory can
be addressed at any time regardless of the state of the
table-select byte. The lower memory and memory table
1 are used to configure the DS1870 and read the status
of the monitors. The lower memory also contains the 32
bytes of user memory. Memory tables 2 and 3 contain
the base potentiometer positions that are used for bias-
ing based on the reading of the internal temperature
sensor. Memory tables 4 and 5 contain the relative off-
sets that are added to the base number as a function of
either the drain voltage or the individual drain current
monitors. See the Memory Map for a complete listing of
registers and the Register Description section for
details about each register.
Password Memory Protection
The DS1870 contains a 2-byte password that allows all
of its EE memory to be write protected until the proper
password is entered into the password entry (PWE)
word (address 78h). This allows factory calibration data
for the bias settings, alarm thresholds, and all the other
EEPROM information to be write protected. The pass-
word is set by writing to the Password register, which is
the first two bytes of memory table 1.
The factory default value for the password is FFFFh,
which is also the factory default value for PWE on
power-up. This means that parts are unlocked at
power-up when they are first received by customers.
The password should be programmed to a value other
than FFFFh to ensure the calibration data is write pro-
tected. The PWE register always reads 0000h regard-
less of its programmed value.
EEPROM Write Disable
Memory locations 20h to 3Fh and Table 1 locations 80h
to A7h are SRAM-shadowed EEPROM. By default
(
SEE = 0) these locations act as ordinary EEPROM. By
setting SEE = 1, these locations begin to function like
SRAM cells, which allow an infinite number of write
cycles without concern of wearing out the EEPROM.
This also eliminates the requirement for the EEPROM
write time. Because changes made with SEE = 1 do not
affect the EEPROM, these changes are not retained
through power cycles. The power-up value is the last
value written with SEE = 0. This function can be used to
limit the number of EEPROM writes during calibration or
to change the monitor thresholds periodically during
normal operation without wearing out the EEPROM. The
SEE bit resides in memory table 1, byte AFh.
Memory Map
The upper part of the memory map is organized into
8-byte or 4-word (2-byte) rows. The beginning address
of the row is shown in the left-most column of the map,
and is equal to the byte 0 or word 0 memory address.
The next byte (Byte 1) is located at the next highest
memory address, and the next word (Word 1) is two
memory addresses greater than the row’s beginning
address. The lower part of the memory map expands
the bytes or the words to show the names of the bits
within the byte/word, or their bit weights (2
X ) for regis-
ters that contain numerical information. Numerical reg-
isters that contain an “S” in the most significant bit are
showing sign extension for 2’s complement numbers.
Descriptions of each byte/bit follow in the Register
Description section.
USER MEMORY;
HI/LO ALARM
THRESHOLDS;
ADC RESULTS;
CONFIGURATION
CONFIGURATION
POT1
TEMP
LUT
POT2
TEMP
LUT
POT1
DRAIN
LUT
POT2
DRAIN
LUT
00h
7Fh
80h
AFh
80h
C7h
80h
C7h
80h
BFh
80h
BFh
MAIN MEMORY
TABLE 1 TABLE 2 TABLE 3 TABLE 4 TABLE 5
TABLE-SELECT
BYTE (7Fh)
SEL
SEL SEL
SEL SEL
Figure 2. Memory Organization