Rainbow Electronics DAB-IMU-C01 - Manual (Page 17)

ADIS16250/ADIS16255
Rev. B | Page 17 of 20
Data-Ready I/O Indicator
The data-ready function provides an indication of updated
output data. The MSC_CTRL register provides the opportu-
nity to configure either of the general-purpose I/O pins (DIO0
and DIO1) as a data-ready indicator signal. After each output
register update, the digital I/O changes states, then returns to its
original state, creating a pulsed waveform. The duty cycle of that
waveform is in between 15% and 35%.
Table 26. MSC_CTRL Register Definition
Address Default Format Access
0x35, 0x34 0x0000 N/A R/W
Table 27. MSC_CTRL Bit Descriptions
Bit Description
15:11 Not used
10 Internal self-test enable
1 = enabled
0 = disabled
9 External negative rotation self-test enable
1 = enabled
0 = disabled
8 External positive rotation self-test enable
1 = enabled
0 = disabled
7:3 Not used
2 Data-ready enable
1 = enabled
0 = disabled
1 Data-ready polarity
1 = active high
0 = active low
0 Data-ready line select
1 = DIO1
0 = DIO0
Self-Test
The MSC_CTRL register also provides a self-test function,
which verifies the MEMS sensor’s mechanical integrity.
There are two different self-test options: (1) internal self-test
and (2) external self-test. The internal test provides a simple,
two-step process for checking the MEMS sensor: (1) start
the process by writing a 1 to Bit 10 in the MSC_CTRL
register and (2) check the result by reading Bit 5 of the
STATUS register, after 35 ms.
The external self-test is a static condition that can be enabled
and disabled. In this test, both positive and negative MEMS
sensor movements are available. After writing to the appropri-
ate control bit, the GYRO_OUT register reflects the changes
after a delay that reflects the sensor signal chain response
time. For example, the standard 52 Hz bandwidth reflects an
exponential response with a time constant of 3.2 ms. If the
bandwidth is reduced externally (capacitor across RATE and FILT)
or internally (increasing the number of filter taps, SENS/AVG), this
time constant increases. For the internal self-test option, increasing
the delay can produce false alarms, since the internal timing for
this function is optimized for maximum bandwidth. The appropri-
ate bit definitions for self-test are listed in Table 26 and Table 27.
Status Conditions
The STATUS register contains the following error-condition flags:
Alarm conditions, self-test status, angular rate over range, SPI
communication failure, control register update failure, and power
supply out of range. See Table 28 and Table 29 for the appropriate
register access and bit assignment for each flag.
The bits assigned for checking power supply range and angular rate
over range automatically reset to 0 when the error condition no
longer exists. The remaining error-flag bits in the STATUS register
require a read in order to return them to 0. Note that a STATUS
register read clears all of the bits to 0.
Table 28. STATUS Register Definition
Address Default Format Access
0x3D, 0x3C 0x0000 N/A Read-only
Table 29. STATUS Bit Descriptions
Bit Description
15:10 Not used
9 Alarm 2 status
1 = active
0 = inactive
8 Alarm 1 status
1 = active
0 = inactive
7:6 Not used
5 Self-test diagnostic error flag
1 = error condition
0 = normal operation
4 Angular rate over range
1 = error condition
0 = normal operation
3 SPI communications failure
1 = error condition
0 = normal operation
2 Control register update failed
1 = error condition
0 = normal operation
1 Power supply above 5.25 V
1 = above 5.25 V
0 = below 5.25 V (normal)
0 Power supply below 4.75 V
1 = below 4.75 V
0 = above 4.75 V (normal)