Rainbow Electronics DS26519 - Manual (Page 70)

DS26519 16-Port T1/E1/J1 Transceiver
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9.9.5.3 Legacy T1 Transmit FDL
It is recommended that the DS26519’s built-in BOC or HDLC controllers be used for most applications requiring
access to the FDL.
Table 9-21 shows the registers related to control of the transmit FDL.
Table 9-21. Registers Related to T1 Transmit FDL
REGISTER
FRAMER 1
ADDRESSES
FUNCTION
Transmit FDL Register ( T1TFDL ) 162h FDL code used to insert transmit FDL.
Transmit Control Register 2 ( T1.TCR2 ) 182h Defines the source of the FDL.
Transmit Latched Status Register 2 ( TLS2 ) 191h Transmit FDL empty bit.
Transmit Interrupt Mask Register 2 ( TIM2 ) 1A1h Mask bit for TFDL empty.
Note: The addresses shown above are for Framer 1.
When enabled with T1.TCR2 .7, the transmit section will shift out into the T1 data stream, either the FDL (in the
ESF framing mode) or the Fs bits (in the D4 framing mode) contained in the Transmit FDL Register ( T1TFDL ).
When a new value is written to the T1TFDL , it will be multiplexed serially (LSB first) into the proper position in the
outgoing T1 data stream. After the full eight bits has been shifted out, the framer will signal the host controller that
the buffer is empty and that more data is needed by setting the
TLS2 .4 bit to a one.
INTB will also toggle low if
enabled via TIM2 .4. The user has 2ms to update the T1TFDL with a new value. If the T1TFDL is not updated, the
old value in the T1TFDL register will be transmitted once again. Note that in this mode, no zero stuffing will be
applied to the FDL data. It is strongly suggested that the HDLC controller be used for FDL messaging applications.
In the D4 framing mode, the framer uses the T1TFDL register to insert the Fs framing pattern. To accomplish this
the T1TFDL register must be programmed to 1Ch and T1.TCR2 .7 should be set to 0 (source Fs data from the
T1TFDL register).
The T1TFDL register contains the Facility Data Link (FDL) information that is to be inserted on a byte basis into the
outgoing T1 data stream. The LSB is transmitted first. In D4 mode, only the lower six bits are used.
9.9.5.4 Legacy T1 Receive FDL
It is recommended that the DS26519’s built-in BOC or HDLC controllers be used for most applications requiring
access to the FDL.
Table 9-22 shows the registers related to the receive FDL.
Table 9-22. Registers Related to T1 Receive FDL
REGISTER
FRAMER 1
ADDRESSES
FUNCTION
Receive FDL Register ( T1RFDL ) 062h FDL code used to receive FDL.
Receive Latched Status Register 7( RLS7 ) 096h Receive FDL full bit is in this register.
Receive Interrupt Mask Register 7( RIM7 ) 0A6h Mask bit for RFDL full.
Note: The addresses shown above are for Framer 1.
In the receive section, the recovered FDL bits or Fs bits are shifted bit-by-bit into the Receive FDL Register
(
T1RFDL ). Since the T1RFDL is 8 bits in length, it will fill up every 2ms (8 times 250
μs). The framer will signal an
external controller that the buffer has filled via the RLS7 .2 bit. If enabled via RIM7 .2, the
INTB pin will toggle low
indicating that the buffer has filled and needs to be read. The user has 2ms to read this data before it is lost. Note
that no zero destuffing is applied to the for the data provided through the
T1RFDL register. The T1RFDL register
reports the incoming Facility Data Link (FDL) or the incoming Fs bits. The LSB is received first. In D4 framing
mode,
T1RFDL updates on multiframe boundaries and reports only the Fs bits.