Rainbow Electronics ATAR862-3 - Manual (Page 18)

18
ATAR862-3
4556B–4BMCU–02/03
ALU The 4-bit ALU performs all the arithmetic, logical, shift and rotate operations with the top
two elements of the expression stack (TOS and TOS-1) and returns the result to the
TOS. The ALU operations affects the carry/borrow and branch flag in the condition code
register (CCR).
Figure 14. ALU Zero-address Operations
I/O Bus The I/O ports and the registers of the peripheral modules are I/O mapped. All communi-
cation between the core and the on-chip peripherals take place via the I/O bus and the
associated I/O control. With the MARC4 IN and OUT instructions, the I/O bus allows a
direct read or write access to one of the 16 primary I/O addresses. More about the I/O
access to the on-chip peripherals is described in the section “Peripheral Modules". The
I/O bus is internal and is not accessible by the customer on the final microcontroller
device, but it is used as the interface for the MARC4 emulation (see also the section
“Emulation").
Instruction Set The MARC4 instruction set is optimized for the high level programming language
qFORTH. Many MARC4 instructions are qFORTH words. This enables the compiler to
generate a fast and compact program code. The CPU has an instruction pipeline allow-
ing the controller to prefetch an instruction from ROM at the same time as the present
instruction is being executed. The MARC4 is a zero-address machine, the instructions
contain only the operation to be performed and no source or destination address fields.
The operations are implicitly performed on the data placed on the stack. There are one-
and two-byte instructions which are executed within 1 to 4 machine cycles. A MARC4
machine cycle is made up of two system clock cycles (SYSCL). Most of the instructions
are only one byte long and are executed in a single machine cycle. For more information
refer to the “MARC4 Programmer’s Guide".
Interrupt Structure The MARC4 can handle interrupts with eight different priority levels. They can be gener-
ated from the internal and external interrupt sources or by a software interrupt from the
CPU itself. Each interrupt level has a hard-wired priority and an associated vector for the
service routine in the ROM (see Table 1). The programmer can postpone the processing
of interrupts by resetting the interrupt enable flag (I) in the CCR. An interrupt occurrence
will still be registered, but the interrupt routine only started after the I-flag is set. All inter-
rupts can be masked, and the priority individually software configured by programming
the appropriate control register of the interrupting module (see section “Peripheral
Modules").
TOS-1
CCR
RAM
TOS-2
SP
TOS-3
TOS
ALU
TOS-4