Rainbow Electronics ATAR862-3 - Manual (Page 67)

67
ATAR862-3
4556B–4BMCU–02/03
3. Timer/SSI combined modes – the SSI used together with Timer 2 or Timer 3 is
capable of performing a variety of data modulation and demodulation functions
(see Timer Section). The modulating data is converted by the SSI into a continu-
ous serial stream of data which is in turn modulated in one of the timer functional
blocks. Serial demodulated data can be serially captured in the SSI and read by
the controller. In the Timer 3 modes 10 and 11 (demodulation modes) the SSI
can only be used as demodulator.
4. Internal Multi-Chip Link pads (MCL) – the SSI can also be used as an interchip
data interface for use in single package multi-chip modules or hybrids. For such
applications, the SSI is provided with two dedicated pads (MCL_SD and
MCL_SC) which act as a two-wire chip-to-chip link. The internal MCL can be
activated by the MCL control bit. Should these MCL pads be used by the SSI, the
standard SD and SC pins are not required and the corresponding Port 4 ports
are available as conventional data ports.
Figure 65. Block Diagram of the Synchronous Serial Interface
General SSI Operation The SSI is comprised essentially of an 8-bit shift register with two associated 8-bit buff-
ers –
the receive buffer (SRB) for capturing the incoming serial data and a transmit
buffer (STB) for intermediate storage of data to be serially output. Both buffers are
directly accessable by software. Transferring the parallel buffer data into and out of the
shift register is controlled automatically by the SSI control, so that both single byte trans-
fers or continuous bit streams can be supported.
The SSI can generate the shift clock (SC) either from one of several on-chip clock
sources or accept an external clock. The external shift clock is output on, or applied to
the Port BP40. Selection of an external clock source is performed by the Serial Clock
Direction control bit (SCD). In the combinational modes, the required clock is selected
by the corresponding timer mode.
The SSI can operate in three data transfer modes – synchronous 8-bit shift mode, a 9-
bit Multi-Chip Link Mode (MCL), containing 8-bit data and 1-bit acknowledge, and a cor-
responding 8-bit MCL mode without acknowledge. In both MCL modes the data
transmission begins after a valid start condition and ends with a valid stop condition.
External SSI clocking is not supported in these modes. The SSI should thus generate
and has full control over the shift clock so that it can always be regarded as an MCL bus
master device.
8-bit Shift Register
MSB LSB
Shift_CL
SO
SIC1 SIC2 SISC
SC
Control
STB SRB
SI
Timer 2 / Timer 3
Output
INT3
SC
I/O-bus
I/O-bus
SSI-Control
TOG2
POUT
T1OUT
SYSCL
SO SI
MCL_SC
SD
MCL_SD
Transmit
Buffer
Receive
Buffer
SCI
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