Rainbow Electronics MAX1068 User Manual
Page 18
MAX1067/MAX1068
prior to the rising edge of CS, cause zeros to be
clocked out of DOUT. The MAX1068 external clock 16-
bit-wide data-transfer mode requires 32 SCLK cycles for
completion (Figure 11).
Force CS high after the conversion result is read. For
maximum throughput, force CS low again to initiate the
next conversion immediately after the specified mini-
mum time (t
CSW
). Forcing CS high in the middle of a
conversion immediately aborts the conversion and
places the MAX1068 in shutdown.
Internal Clock 8-Bit-Wide Data-Transfer and
Scan Mode (MAX1067 and MAX1068)
Force DSPR high and DSEL low (MAX1068) for the SPI/
QSPI/MICROWIRE-interface mode. The falling edge of
CS wakes the analog circuitry and allows SCLK to
clock in data (Figure 12). DOUT changes from high-Z
to logic low after CS is brought low. Input data latches
on the rising edge of SCLK. The command/configura-
tion/control register begins reading DIN on the first
SCLK rising edge and ends on the rising edge of the
8th SCLK cycle. The MAX1067/MAX1068 select the
proper channel for conversion on the rising edge of the
3rd SCLK cycle. The internal oscillator activates 125ns
after the rising edge of the 8th SCLK cycle. Turn off the
external clock while the internal clock is on. Turning off
SCLK ensures the lowest noise performance during
acquisition. Acquisition begins on the 2nd rising edge
of the internal clock and ends on the falling edge of the
6th internal clock cycle. Each bit of the conversion
result shifts into memory as it becomes available. The
conversion result is available (MSB first) at DOUT on
the falling edge of EOC. The internal oscillator and ana-
log circuitry are shut down on the high-to-low EOC tran-
Multichannel, 14-Bit, 200ksps Analog-to-Digital
Converters
18
______________________________________________________________________________________
DOUT
CS
SCLK
DIN
DSPR
DSEL
0
MSB
LSB
MSB
LSB
S1 S0
ADC
STATE
16
24
32
1
8
X
X
X
X
X
X
X
X
X = DON
,
T CARE
t
ACQ
IDLE
t
CONV
Figure 11. SPI External Clock Mode, 16-Bit Data-Transfer Mode, Conversion Timing (MAX1068 Only)
DOUT
CS
SCLK
DIN
EOC
1
MSB
LSB
LSB
S1 S0
X
t
ACQ
IDLE
t
CONV
POWER-DOWN
ADC
STATE
X = DON
,
T CARE
DSPR = DV
DD
, DSEL = GND (MAX1068 ONLY)
INTERNAL
CLK
1
8
2
6
25
16
9
24
• • •
MSB
Figure 12. SPI Internal Clock Mode, 8-Bit Data-Transfer Mode, Conversion Timing