Rainbow Electronics MAX1068 User Manual
Page 28
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
where V
1
is the fundamental amplitude and V
2
through
V
5
are the 2nd- through 5th-order harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next-largest fre-
quency component.
Supplies, Layout, Grounding, and
Bypassing
Use printed circuit (PC) boards with separate analog
and digital ground planes. Do not use wire-wrap
boards. Connect the two ground planes together at the
MAX1067/MAX1068 AGND terminal. Isolate the digital
supply from the analog with a low-value resistor (10
Ω)
or ferrite bead when the analog and digital supplies
come from the same source (Figure 25).
Constraints on sequencing the power supplies and
inputs are as follows:
• Apply AGND before DGND.
• Apply AIN_ and REF after AV
DD
and AGND are
present.
• DV
DD
is independent of the supply sequencing.
Ensure that digital return currents do not pass through
the analog ground and that return-current paths are low
impedance. A 5mA current flowing through a PC board
ground trace impedance of only 0.05
Ω creates an error
voltage of about 250µV and a 1 LSB error with a +4.096V
full-scale system.
The board layout should ensure that digital and analog
signal lines are kept separate. Do not run analog and dig-
ital lines (especially the SCLK and DOUT) parallel to one
another. If one must cross another, do so at right angles.
The ADC’s high-speed comparator is sensitive to high-
frequency noise on the AV
DD
power supply. Bypass an
excessively noisy supply to the analog ground plane
with a 0.1µF capacitor in parallel with a 1µF to 10µF
low-ESR capacitor. Keep capacitor leads short for best
supply-noise rejection.
T
+ V
+ V
+ V
2
3
2
4
2
5
2
1
HD
V
V
=
×
20
2
log
MAX1067/MAX1068
Multichannel, 14-Bit, 200ksps Analog-to-Digital
Converters
28
______________________________________________________________________________________
SCLK
DOUT
AGND
DGND
AIN_
REF
AV
DD
DV
DD
DOUT
SCLK
CS
AIN_
+5V
10
Ω
1
µF
0.1
µF
0.1
µF
GND
MAX1067
MAX1068
AGND
CS
Figure 25. Powering AV
DD
and DV
DD
from a Single Supply