Rainbow Electronics MAX1068 User Manual
Page 22
MAX1067/MAX1068
4.8MHz (the maximum clock frequency). For lower
clock frequencies, ensure the minimum high and low
times are at least 93ns. External-clock-mode conver-
sions with SCLK rates less than 125kHz can reduce
accuracy due to leakage of the sampling capacitor.
The input data latches on the falling edge of SCLK. The
command/configuration/control register starts reading
data in on the falling edge of the first SCLK cycle imme-
diately following the falling edge of the frame sync
pulse and ends on the falling edge of the 16th SCLK
cycle. The MAX1068 selects the proper channel for
conversion on the falling edge of the 3rd clock cycle
and begins acquisition. Acquisition continues until the
rising edge of the 15th clock cycle. The MAX1068 sam-
ples the input on the rising edge of the 15th clock cycle.
On the rising edge of the 16th clock cycle, the MAX1068
outputs a frame sync pulse at DSPX. The frame sync
pulse alerts the DSP that the conversion results are
about to be output at DOUT (MSB first) starting on the
rising edge of the 17th clock pulse. To read the entire
conversion result, 16 SCLK cycles are needed. Extra
clock pulses, occuring after the conversion result has
been clocked out and prior to the next rising edge of
DSPR, cause zeros to be clocked out of DOUT. The
MAX1068 external clock, DSP 16-bit-wide data-transfer
mode requires 32 clock cycles to complete.
Begin a new conversion by sending a new frame sync
pulse to DSPR followed by new configuration data.
Send the new DSPR pulse immediately after reading
the conversion result to realize maximum throughput.
Sending a new frame sync pulse in the middle of a con-
version immediately aborts the current conversion and
begins a new one. A rising edge on CS in the middle of
a conversion aborts the current conversion and places
the MAX1068 in shutdown.
Multichannel, 14-Bit, 200ksps Analog-to-Digital
Converters
22
______________________________________________________________________________________
DOUT
CS
DSPR
SCLK
DIN
DSPX
0
MSB
LSB
MSB
LSB
S1
S0
t
ACQ
IDLE
t
CONV
ADC
STATE
1
8
16
24
Figure 17. DSP External Clock Mode, 8-Bit Data-Transfer Mode, Conversion Timing (MAX1068 Only)
DOUT
CS
SCLK
DIN
0
MSB
LSB
MSB
LSB
S1
ADC
STATE
16
24
32
1
8
X
X
X
X
X
X
X
X
X = DON
,
T CARE
t
ACQ
IDLE
t
CONV
DSPR
DSPX
S0
Figure 18. DSP External Clock Mode, 16-Bit Data-Transfer Mode, Conversion Timing (MAX1068 Only)