SENA Parani-BCD100 - Manual (Page 14)

PARANI-BCD100
Page 14 of 22
4.5 I/O Parallel Ports
PIO lines can be configured through software to have either weak or strong pull-downs. All PIO lines are
configured as inputs with weak pull-downs at reset.
Any of the PIO lines can be configured as interrupt request lines or as wake-up lines from sleep modes.
PIO_6 or PIO_2 can be configured as a request line for an external clock source. This is useful when the
clock to BCD100 is provided from a system ASIC (Application Specific Integrated Circuit). Using
PSKEY_CLOCK_REQUEST_ENABLE (0x246), this terminal can be configured to be low when BCD100 is in
Deep Sleep and high when a clock is required. The clock must be supplied within 4ms of the rising edge of
PIO_6 or PIO_2 to avoid losing timing accuracy in certain Bluetooth operating modes.
BCD100 has three general purpose analogue interface pins, AIO_0, AIO_1 and AIO_2. These are used to
access internal circuitry and control signals. One pin is allocated to decoupling for the on-chip band gap
reference voltage, the other two may be configured to provide additional functionality.
4.6 Reset Interface
BCD100 may be reset from several sources: RESETB pin, power on reset, a UART break character or via a
software configured watchdog timer.
The RESETB pin is an active low reset and is internally filtered using the internal low frequency clock
oscillator. A reset will be performed between 1.5 and 4.0ms following RESETB being active. It is
recommended that RESETB be applied for a period greater than 5ms.
The power on reset occurs when the VDD_CORE supply falls below typically 1.5V and is released
when VDD_CORE rises above typically 1.6V.
At reset the digital I/O pins are set to inputs for bi-directional pins and outputs are tri-state. The
PIOs have weak pull-downs.