GE Industrial Solutions ASPMETER commiss - Manual (Page 15)

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COMMISSIONING GUIDE ASPMETER
DET-757 PAGE 15 ©2011 For technical support please contact 10111
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CONFIGURING ALARM REGISTERS
Latching alarms
Once the alarm threshold is crossed into an alarm state and after the associated
Alarm Timer expires, the corresponding latching status bit is set and is not reset until
the status bit is manually cleared by writing the alarm status register or resetting
Latching alarms even if the signal is no longer in an alarm state. The alarm is also
cleared if the threshold is changed.
Non-Latching alarms
Once the alarm threshold is crossed into an alarm state the corresponding Non-
Latching status bit is set. The Non-Latching status bit is cleared once the signal
crosses the threshold (plus hysteresis) out of an alarm state.
Alarm Timers
These timers control entry into an alarm state. All channels use the same global per-
panel timers; per-panel timers only apply to latching alarms.
Registers 165-170:
• High-High Latching Alarm Time Delay
• High Latching Alarm Time Delay
• Low Latching Alarm Time Delay
• Low-Low Latching Alarm Time Delay
• Latching Alarm ON Time (when current is above Low-Low alarm then ON
state is declared)
• Latching Alarm OFF State (current is below Low-Low alarm and ON state
was declared)
Alarm Thresholds
All values are expressed as a percentage of breaker size. All channels use the same
global per-panel values. An entry of 0% will disable the alarm for that channel.
Hysteresis only applies to Non-Latching alarms.
Registers 171-177:
• High-High Latching Alarm Threshold
• High Alarm Latching Alarm Threshold
• Low Alarm Latching Alarm Threshold
• Low Low Latching Alarm Threshold
• Non-Latching High Threshold
• Non-Latching Low Threshold
• Hysteresis (0-100% percent of setpoint; non-latching alarms only)
Branch Current Alarms
Registers 178-219:
Latching Alarms are cleared by writing a 0 to its alarm bit. A write to a Non-Latching
alarm is ignored.
• Bit 0: High High Latching Alarm
• Bit 1: High Latching Alarm
• Bit 2: Low Latching Alarm
• Bit 3: Low Low Latching Alarm
• Bit 4: Latching Alarm off state declared
• Bit 5-7: Reserved for future use (reads 0)
• Bit 8: High Non-Latching Alarm
• Bit 9: Low Non-Latching Alarm
• Bit 10-15: Reserved for future use (reads 0)
AUX Current Alarms
Registers 220-223:
Latching Alarms are cleared by writing a 0 to its alarm bit.
• Bit 0: High High Latching Alarm
• Bit 1: High Latching Alarm
• Bit 2: Low Latching Alarm
• Bit 3: Low Low Latching Alarm
• Bit 4: Latching Alarm Off
• Bit 5-7: Reserved for future use (reads 0)
• Bit 8: High Non-Latching Alarm
• Bit 9: Low Non-Latching Alarm
• Bit 10-15: Reserved for future use (reads 0)
Line-to-Line Voltage Alarm Timers
These timers control entry into an alarm state. All channels use the same
global per-panel channels. Voltage alarms are global; settings and alarms
are shared between both panels for main boards with four ribbon cable
connections.
Registers 236-237:
• Overvoltage Alarm Timer
• Undervoltage Alarm Timer
Line-to-Line Voltage Alarm Thresholds
Thresholds are expressed as Volts. An entry of 0 disables that alarm for all
channels.
Registers 238-240:
• Overvoltage Alarm Threshold
• Undervoltage Alarm Threshold
• Voltage Alarm Hysteresis (percentage of setpoint)
Line-to-Line Voltage Alarms
Registers 241-243:
• Latching Alarms are cleared by writing a 0 to its alarm bit.
• Bit 0: High Latching Alarm
• Bit 1: Low Latching Alarm
• Bit 2-7: Reserved for future use (reads 0)
• Bit 8: High Non-Latching Alarm
• Bit 9: Low Non-Latching Alarm
• Bit 10-15: Reserved for future use (reads 0)