Asus Barebone System Vintage-PE2 - Manual (Page 83)

A S U S V i n t a g e - P E 2 A S U S V i n t a g e - P E 2 A S U S V i n t a g e - P E 2 A S U S V i n t a g e - P E 2 A S U S V i n t a g e - P E 2 5 - 2 1 5 - 2 1 5 - 2 1 5 - 2 1 5 - 2 1
5.4.3 5.4.3 5.4.3 5.4.3 5.4.3 Chipset Chipset Chipset Chipset Chipset
The Chipset menu allows you to change the advanced chipset settings.
Select an item then press <Enter> to display the sub-menu.
Advanced Chipset Settings
Configure DRAM Timing by SPD [Enabled]
Pre-allocated Graphics Memory [Enabled, 8MB]
Graphics Memory Type [Auto]
Enable or disable
DRAM timing.
Configure DRAM Timing by SPD [Enabled] Configure DRAM Timing by SPD [Enabled] Configure DRAM Timing by SPD [Enabled] Configure DRAM Timing by SPD [Enabled] Configure DRAM Timing by SPD [Enabled]
When this item is enabled, the DRAM timing parameters are set according
to the DRAM SPD (Serial Presence Detect). When disabled, you can
manually set the DRAM timing parameters through the DRAM sub-items.
The following sub-items appear when this item is Disabled. Configuration
options: [Disabled] [Enabled]
DRAM CAS# Latency [3 Clocks]
Controls the latency between the SDRAM read command and the time
the data actually becomes available.
Configuration options: [3 Clocks] [2.5 Clocks] [2 Clocks]
DRAM RAS# Precharge [4 Clocks]
Controls the idle clocks after issuing a precharge command to the DDR
SDRAM. Configuration options: [2 Clocks] [3 Clocks] [4 Clocks]
[5
Clocks]
DRAM RAS# to CAS# Delay [4 Clocks]
Controls the latency between the DDR SDRAM active command and
the read/write command. Configuration options: [2 Clocks]
[3 Clocks] [4 Clocks] [5 Clocks]
DRAM RAS# Activate to Precharge Delay [15 Clocks]
Configuration options: [4 Clocks] [5 Clocks] ~ [15 Clocks]
DRAM Burst Length [8]
Sets the DRAM Burst Length. Configuration options: [4] [8]