Ampro Corporation Single Board Computer Littleboard 550 - Manual (Page 76)

Chapter 4 BIOS Setup
70 Reference Manual LittleBoard 550
Memory Control Options
• Memory
♦ Memory Test – [Fast], [Standard], or [Exhaustive]
• If this field is set to [Fast], only basic memory tests are performed during POST to shorten
POST time.
• If this field is set to [Standard], more than basic tests are performed, but POST time is
increased.
• If this field is set to [Exhaustive], more rigorous tests are performed on memory, but this
takes a significant amount of time for POST to complete.
♦ Memory Hole – [Disabled], [1MB], or [2MB]
This field specifies the size of an optional memory hole, below 16MB. Access to the memory
addresses inside the memory hole region are forwarded to the PC/104 bus, where memory
mapped PC/104 devices have access.
♦ Shadow D000-D3FF – [Disabled] or [Enabled]
These Shadow fields specify if BIOS option ROMs in the indicated segments should be
shadowed to RAM. Shadowing option ROMs can potentially speed up the operation of the
system. The indicated segments are only for option ROMs present on add-on PC/104 and
PC/104-Plus cards.
♦ Shadow D400-D7FF – [Disabled] or [Enabled]
♦ Shadow D800-DBFF – [Disabled] or [Enabled]
♦ Shadow DC00-DFFF – [Disabled] or [Enabled]
• DRAM
NOTE The DRAM clock frequency can never be set higher than
the CPU’s Front Side Bus (FSB) clock frequency,
regardless of the SPD or PC100 setting.
♦ DRAM Clock Frequency – [SPD] or [PC100]
This field specifies the DRAM clock frequency.
• If this field is set to SPD (Serial Presence Detect), then the DRAM clock is set using the
information read from the SPD(s) on the DRAM module(s).
• If this field is set to PC100, the clock will override the DRAM SPD information and force
the DRAM clock to 100MHz.
♦ DRAM CAS Latency – [SPD], [CAS 3], or [CAS 2]
This field specifies the DRAM CAS (Column Address Strobe) Latency
• If this field is set to SPD, then the DRAM CAS latency is set using the information read
from the SPD(s) on the DRAM module(s).
• If this field is set to CAS 2 or CAS 3, the setting will override the DRAM SPD
information and force the DRAM CAS latency to the specified value.