QPHY-DDR3 Software Option
917717 Rev C
5
VIH(dc), minimum DC input logic high ....................................................................................................................... 37
VIL(ac), maximum AC input logic low ......................................................................................................................... 38
VIL(dc), minimum DC input logic low ......................................................................................................................... 38
Read Bursts (Outputs) ...................................................................................................................................... 38
SRQ (Output Slew Rate) ................................................................................................................................................ 38
SRQr and SRQf ......................................................................................................................................................... 38
Timing Tests ............................................................................................................................................................. 38
Read Bursts ...................................................................................................................................................... 38
tDQSQ, DQS-DQ Skew for DQS and Associated DQ Signals ....................................................................................... 38
tQH, DQ/DQS Output Hold Time From DQS.................................................................................................................. 39
tDQSCK, DQS Output Access Time from CK/CK # ....................................................................................................... 39
Write Bursts ...................................................................................................................................................... 41
tDQSS, DQS latching rising transitions to associated CK edge ..................................................................................... 41
tDQSH, DQS Input High Pulse Width ............................................................................................................................. 41
tDQSL, DQS Input Low Pulse Width .............................................................................................................................. 41
tDSS, DQS Falling Edge to CK Setup Time ..................................................................................................... 42
tDSH, DQS Falling Edge Hold Time from CK ................................................................................................... 42
tDS(base), DQ and DM Input Setup Time ........................................................................................................ 42
tDH(base), DQ and DM Input Hold Time .......................................................................................................... 42
Four Probe tests measurements using ADDR/CTL ................................................................................................. 42
tIS /tIH (base) - Address and Control Input Setup Time (Hold Time) ............................................................... 42
tIPW, Control and Address Input pulse width for each input ............................................................................ 43
VIX(ac), AC Differential Input Cross Point Voltage ........................................................................................... 44