KEPCO BIT 232F User Manual

Page 32

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A-2

BIT 232 022800

FIGURE A-2. *ESE — STANDARD EVENT STATUS ENABLE COMMAND

FIGURE A-3. *ESE? — STANDARD EVENT STATUS ENABLE QUERY

Syntax:

*ESE <integer>
<integer> = positive whole number: 0 to 255 per

STANDARD EVENT STATUS ENABLE REGISTER BITS

table below.

Function:

Sets ESE (standard Event Status Enable) register bits to enable the Standard events to be summa-
rized in the Status Byte register (1 = set = enable function, 0 = reset = disable function).

Response:

Not applicable

Description:

Contents of Standard Event Status Enable register (*ESE) determine which bits of Standard Event
Status register (*ESR) are enabled, allowing them to be summarized in the Status Byte register
(*STB). All of the enabled events of the Standard Event Status Enable Register are logically ORed
to cause ESB (bit 5) of the Status Byte Register to be set.

Example:

*ESE 49

Power supply enables bits 0, 4 and 5) allowing command error, execution error
and operation complete conditions to be recorded in the Event Status Register.

STANDARD EVENT STATUS ENABLE REGISTER BITS

CONDITION

NU

NU

CME

EXE

DDE

QUE

NU

OPC

BIT

7

6

5

4

3

2

1

0

VALUE

128

64

32

16

8

4

2

1

NU

(Not Used)

CME

Command Error

EXE

Execution Error

DDE

Device Dependent Error

QUE

Query Error

OPC

Operation Complete

*ESE

Syntax:

*ESE?

Response:

<integer> value per

STANDARD EVENT STATUS ENABLE REGISTER BITS

table below.

Function:

Returns the status of the Standard Event Status Enable Register

Description:

Contents of Standard Event Status Enable register (*ESE) determine which bits of Standard Event
Status register (*ESR) are enabled, allowing them to be summarized in the Status Byte register
(*STB). All of the enabled events of the Standard Event Status Enable Register are logically ORed to
cause ESB (bit 5) of the Status Byte Register to be set (1 = set = enable function, 0 = reset = disable
function).

Example:

*ESE 49

Power Supply enables bits 0, 4 and 5

*ESE?

Controller reads <value> 49, verifying that bits 0, 4 and 5 have been enabled.

STANDARD EVENT STATUS ENABLE REGISTER BITS

CONDITION

NU

NU

CME

EXE

DDE

QUE

NU

OPC

BIT

7

6

5

4

3

2

1

0

VALUE

128

64

32

16

8

4

2

1

*ESE?

NU

(Not Used)

CME

Command Error

EXE

Execution Error

DDE

Device Dependent Error

QUE

Query Error

OPC

Operation Complete

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