Sony PCV-J100 - Manual (Page 88)

VAIO® Reference Manual 74
Chip Configuration Sub-Menu
SDRAM Configuration [By SPD]
User Define
7ns (143MHz)
8ns (125MHz)
SDRAM CAS Latency [3T]
SDRAM RAS to CAS Delay [3T]
SDRAM RAS Precharge Time [3T]
SDRAM Cycle Time (Tras, Trc) [5T, 7T]
6T, 8T
SDRAM Page Closing Policy [All Banks]
One Bank
CPU Latency Timer [Enabled]
Disabled
On-board VGA [Enabled]
Disabled
Display Cache Paging Mode [Page open]
Page close
Video Memory Cache Mode [UC]
USWC
Memory Hole At 15M-16M [Disabled]
Enabled
PCI 2.1 Support [Enabled]
Disabled
High Priority PCI Mode [Enabled]
Disabled
Onboard PCI IDE Enable [Both]
Primary
Secondary
Disabled