Cirrus Logic CS42L52 - Manual (Page 7)

DS680F2 7
CS42L52
3/1/13
9.1 Power Supply and Grounding ......................................................................................................... 77
9.2 QFN Thermal Pad .......................................................................................................................... 77
10. ADC AND DAC DIGITAL FILTERS .................................................................................................. 78
11. PARAMETER DEFINITIONS .............................................................................................................. 79
12. PACKAGE DIMENSIONS .................................................................................................................. 80
THERMAL CHARACTERISTICS .......................................................................................................... 80
13. ORDERING INFORMATION .............................................................................................................. 81
14. REFERENCES .................................................................................................................................... 81
15. REVISION HISTORY .......................................................................................................................... 81
LIST OF TABLES
Table 1. MCLK, LRCK Quick Decode ....................................................................................................... 34
LIST OF FIGURES
Figure 1. Typical Connection Diagram ...................................................................................................... 11
Figure 2. Headphone Output Test Load .................................................................................................... 18
Figure 3. Serial Audio Interface Timing ..................................................................................................... 20
Figure 4. Control Port Timing - I²C ............................................................................................................ 21
Figure 5. Analog Input Signal Flow ........................................................................................................... 25
Figure 6. Single-Ended MIC Configuration ............................................................................................... 26
Figure 7. Differential MIC Configuration .................................................................................................... 26
Figure 8. ALC ............................................................................................................................................ 27
Figure 9. Noise Gate Attenuation .............................................................................................................. 27
Figure 10. DSP Engine Signal Flow .......................................................................................................... 28
Figure 11. PWM Output Stage .................................................................................................................. 29
Figure 12. Analog Output Stage ................................................................................................................ 29
Figure 13. Beep Configuration Options ..................................................................................................... 30
Figure 14. Peak Detect and Limiter ........................................................................................................... 31
Figure 15. Battery Compensation ............................................................................................................. 33
Figure 16. I²S Format ................................................................................................................................ 35
Figure 17. Left-Justified Format ................................................................................................................ 35
Figure 18. Right-Justified Format (DAC only) ........................................................................................... 35
Figure 19. DSP Mode Format) .................................................................................................................. 36
Figure 20. Control Port Timing, I²C Write .................................................................................................. 38
Figure 21. Control Port Timing, I²C Read .................................................................................................. 39
Figure 22. THD+N vs. Output Power per Channel at 1.8 V (16
 load) ................................................... 74
Figure 23. THD+N vs. Output Power per Channel at 2.5 V (16
 load) ................................................... 74
Figure 24. THD+N vs. Output Power per Channel at 1.8 V (32
 load) ................................................... 75
Figure 25. THD+N vs. Output Power per Channel at 2.5 V (32
 load) ................................................... 75
Figure 26. ADC Passband Ripple ............................................................................................................. 78
Figure 27. ADC Stopband Rejection ......................................................................................................... 78
Figure 28. ADC Transition Band ............................................................................................................... 78
Figure 29. ADC Transition Band (Detail) ................................................................................................... 78
Figure 30. DAC Passband Ripple ............................................................................................................. 78
Figure 31. DAC Stopband ......................................................................................................................... 78
Figure 32. DAC Transition Band ............................................................................................................... 78
Figure 33. DAC Transition Band (Detail) ................................................................................................... 78