DS810UM6
Copyright 2013 Cirrus Logic, Inc.
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CS4953x4/CS4970x4 System Designer’s Guide
Table 3-2. Bursty Data Input (BDI) Pins .......................................................................................................3-3
Table 3-3. Input Data Format Configuration (Input Parameter A) ................................................................3-5
Table 3-4. Input SCLK Polarity Configuration (Input Parameter B) ..............................................................3-5
Table 3-5. Input LRCLK Polarity Configuration (Input Parameter C) ...........................................................3-6
Table 3-6. Input DAI Mode Configuration (Input Parameter D) ....................................................................3-6
Table 3-7. DSDl Audio Input Port .................................................................................................................3-7
Table 4-1. Digital Audio Output (DAO1 & DAO2) Pins .................................................................................4-1
Table 4-2. Output Clock Mode Configuration (Parameter A) .......................................................................4-5
Table 4-3. DAO1 & DAO2 Clocking Relationship Configuration (Parameter B) ...........................................4-5
Table 4-4. Output DAO_SCLK/LRCLK Configuration (Parameter C) ..........................................................4-5
Table 4-5. Output Data Format Configuration (Parameter D) ......................................................................4-8
Table 4-6. Output DAO_LRCLK Polarity Configuration (Parameter E) ........................................................4-9
Table 4-7. Output DAO_SCLK Polarity Configuration (Parameter F) ..........................................................4-9
Table 4-8. Output Channel Configuration (Parameter G) .............................................................................4-9
Table 4-9. S/PDIF Transmitter Pins ...........................................................................................................4-10
Table 4-10. S/PDIF Transmitter Configuration ...........................................................................................4-10
Table 4-11. DSP Bypass Configuration ......................................................................................................4-11
Table 5-1. SDRAM Interface Signals ...........................................................................................................5-2
Table 5-2. SDRAM Interface Parameters .....................................................................................................5-4
Table 7-2. DSP_LAST_ACCN_MSG Messages ..........................................................................................7-5
Table 7-1. DSP_AUTODETECT_MSG Messages .......................................................................................7-5
Table 7-3. Microcontroller Interface API .......................................................................................................7-7
Table 7-4. DSP_CFG_xxx Firmware Configuration Registers .....................................................................7-7
Table 7-5. Firmware Status Registers ........................................................................................................7-12
Table 7-6. Legacy Audio Manager .............................................................................................................7-14
Table 7-7. OS Module Variables ................................................................................................................7-17
Table 9-1. Translation from Input Sources to Board Configuration Values ..................................................9-7
