Cirrus Logic CS4970x4 - Manual (Page 16)

CS4953x4/CS4970x4 Chip Functional Overview
CS4953x4/CS4970x4 System Designer’s Guide
DS810UM6 Copyright 2013 Cirrus Logic, Inc P-5
for compressed data input, custom internal hardware is enabled that off-loads some pre-processing of the
incoming stream to help maximize the MIPS available in the DSP core for user-customized applications.
P.3.7 Direct Stream Digital (DSD) Controller
The DSD controller for the CS4953x4/CS4970x4 also has a DSD controller which allows the DSP to be
integrated into a system that supports SACD audio. The DSD controller pins are shared with the DAI1 and
DAI2 ports. The DSD port consists of a bit clock (DSD_CLK) and six DSD data inputs (DSD[5:0]).
P.3.8 General Purpose I/O
A 32-bit general-purpose I/O (GPIO) port is provided on the CS4953x4/CS4970x4 DSPs to enhance
system flexibility. Many of the functional pins can be used for either GPIO or peripherals.
Each GPIO pin can be individually configured as an output, an input, or an input with interrupt. A GPIO
interrupt can be triggered on a rising edge (0-to-1 transition), falling edge (1-to-0 transition), or logic level
(either 0 or 1). Each pin configured as an input with interrupt can be assigned its own interrupt trigger
condition. All GPIOs share a common interrupt vector.
P.3.9 Serial Control Ports (SPI
™
or I 2 C
™
Standards)
The CS4953x4/CS4970x4 have two serial control ports (SCP) that support SPI
™
and I
2
C
™
Master/Slave
communication modes. The serial control port allows external devices such as microcontrollers to
communicate with the CS4953x4/CS4970x4 chips through either I
2
C or SPI serial communication
standards and can be configured as either a Master or a Slave.
The CS4953x4/CS4970x4 SPI and I
2
C serial communication modes are identical from a functional
standpoint. The main difference between the two is the protocol being implemented between the
CS4953x4/CS4970x4 and the external device. In addition, the I
2
C Slave has a true I
2
C mode that utilizes
data flow mechanisms inherent to the I
2
C protocol. If this mode is enabled, the I
2
C Slave will hold
SCP1_CLK low to delay a transfer as needed.
By default, SCP1 is configured as a Slave for external device-controlled data transfers. As a Slave, it
cannot drive the clock signal nor initiate data transfers.
By default, SCP2 is configured as a Master to access a SPI Flash for either booting the DSP or retrieving
configuration information. As a Master, it can drive the clock signal at up to 1/2 of the DSP’s core clock
speed.
The CS4953x4/CS4970x4 has two additional serial communication pins not specified in either the I
2
C or
SPI specification. The port uses the SCP1_IRQ pin to indicate that a read message is ready for the host.
The port uses the SCP1_BSY pin to warn the host to pause communication.
P.3.10 SDRAM Controller
The CS4953x4/CS4970x4 supports a glueless external SDRAM interface to extend the data memory of
the DSP during runtime. The SDRAM controller provides 2-port access to X and Y memory space, a
quad-word read buffer, and a double-buffered quad-word write buffer. One SDRAM controller port is
dedicated to P memory space and the second port is shared by X and Y memories. The X/Y port has dual
write buffers and a single read buffer, and the P memory port has a single read buffer. One of these
buffers is four 32-bit words (128 bits). Every “miss” to the read buffer will cause the SDRAM controller to
burst eight 16-bit reads on the SDRAM interface. The SDRAM controller supports SDRAMs from 2 MB to
64 MB with various row, bank, and column configurations. The SDRAM controller runs synchronous to the
DSP core clock, which is the global chip clock.