Cirrus Logic CS4970x4 - Manual (Page 50)

SPI Port
CS4953x4/CS4970x4 System Designer’s Guide
DS810UM6 Copyright 2013 Cirrus Logic, Inc 2-4
signal is low. The bus is free only when all Slave SCP1_CS signals are high. A high-to-low transition on
the SCP1_CS line defines an SPI Start condition. A low-to-high transition on the SCP1_CS line defines an
SPI Stop condition. Start and Stop conditions are always generated by the Master. The bus is considered
to be busy after the Start condition. The bus is considered to be free again following the Stop condition.
The data bits of the SCP1_MOSI and SCP1_MISO line are valid on the rising edge of SCP1_CLK. It is the
Slave’s responsibility to accept or supply bytes on the bus at the rate at which the Master is driving
SCP1_CLK.
All data put on the SCP1_MOSI and SCP1_MISO lines must be in 8-bit bytes. The number of bytes that
can be transmitted per transfer is unrestricted. Data is transferred with the most-significant bit (MSB) first.
For the CS4953x4/CS4970x4 Slave SPI port, the first byte is an address byte that is always sent by the
Master after a Start condition. This address byte is an “I
2 C-type” command of a 7-bit address + a R/W bit.
The 7-bit SPI address is 1000000b (0x80).
If the SPI transaction is a write from Master to the CS4953x4/CS4970x4 (R/W = 0, Address = 0x80), then
the Master will clock the SCP1_CLK signal and drive the SCP1_MOSI signal with data bytes for the
CS4953x4/CS4970x4 to read. If the SPI transaction is a read to the Master from the CS4953x4/
CS4970x4 (R/W = 1, Address = 0x81), then the Master will drive the SCP1_CLK signal and read the
SCP1_MISO signal with the data bytes from the CS4953x4/CS4970x4.
2.4.2.1 SCP1_BSY Behavior
The SCP1_BSY signal is not part of the SPI protocol, but it is provided so that the Slave can signal to the
Master that it cannot receive any more data. A falling edge of the SCP1_BSY signal indicates the Master
must halt transmission. Once the SCP1_BSY signal goes high, the suspended transaction may continue.
The host must obey the SCP1_BSY pin or control data will be lost
2.4.3 SPI Messaging
Messaging to the CS4953x4/CS4970x4 using the SPI bus requires usage of all the information provided
in the SPI Bus Description and Bus Dynamics above. For control and application image downloading, SPI
transactions to the CS4953x4/CS4970x4 will involve 4-byte words. A detailed description of the serial SPI
communication mode is provided in this section. This includes:
• A flow diagram and description for a serial SPI write
• A flow diagram and description for a serial SPI read
2.4.3.1 Performing a Serial SPI Write
Information provided in this section is intended as a functional description indicating how to perform an
SPI write from an external device (Master) to the CS4953x4/CS4970x4 DSP (Slave). The system
designer must ensure that all timing constraints of the SPI Write Cycle are met (see the CS4953x4/
CS4970x4 datasheet for timing specifications). When performing an SPI write, the same protocol is used
whether writing single-word messages to the boot firmware, writing multiple-word overlay images to the
boot firmware, or writing multiple-word messages to the application firmware. The example shown in this
section can be generalized to fit any SPI write situation.
The flow diagram shown in Figure 2-3 illustrates the sequence of events that define the SPI write
protocol.
Figure 2-4 describes the Serial SPI Write protocol.