Cirrus Logic CS5378 - Manual (Page 16)

CS5378
DS639F3 16
SWITCHING CHARACTERISTICS
CLK, SYNC, MCLK, MSYNC, and MDATA
Notes: 3. PLL bypass mode. The PLL generates a 32.768 MHz master clock when enabled.
4. Sampling synchronization between multiple CS5378 devices receiving identical SYNC signals.
Parameter Symbol Min Typ Max Unit
Master Clock Frequency (Note 3) CLK 32 32.768 33 MHz
Master Clock Duty Cycle DTY 40 - 60 %
Master Clock Rise Time t
RISE
- - 20 ns
Master Clock Fall Time t
FALL
- - 20 ns
Master Clock Jitter JTR - - 300 ps
Synchronization after SYNC rising (Note 4) SYNC -2 - 2 μs
MSYNC Setup Time to MCLK rising t
mss
20 - - ns
MCLK rising to Valid MDATA t
mdv
- - 75 ns
MSYNC falling to MCLK rising t
msf
20 - - ns
MSYNC
MCLK
MDATA
Figure 7. SYNC, MCLK, MSYNC, MDATA Interface Timing
t
msd
t
msd
t
msh
Data1 Data2
SYNC
f
MCLK
2.048 MHz 1.024 MHz
t
msd
= T
MCLK
/ 4 t
msd
= 122 ns t
msd
= 244 ns
t
msh
= T
MCLK
t
msh
= 488 ns t
msh
= 976 ns
Note: SYNC input latched on MCLK rising edge. MSYNC output triggered by MCLK falling edge.