Cirrus Logic CS5378 - Manual (Page 39)

CS5378
DS639F3 39
11.2.2 Output Word Rate
The CS5378 digital filter supports output word rates (OWRs) between 4000 SPS and 1 SPS. The output
word rate is selected by the DEC bits in the FILTCFG register.
When taking data directly from the SINC filter, the decimation of the FIR1 and FIR2 stages is bypassed
and the actual output word rate is multiplied by a factor of eight compared with the register selection. When
taking data directly from FIR1, the decimation of the FIR2 stage is bypassed and the actual output word
rate is multiplied by a factor of two. Data taken from the FIR2, IIR1, IIR2, or IIR3 filtering stages is output
at the selected rate.
11.2.3 Digital Filter Clock
The digital filter clock rate is programmable between 8.192 MHz and 32 kHz by bits in the CONFIG reg-
ister.
Computation Cycles
The minimum digital filter clock rate for a configuration depends on the computation cycles required to
complete digital filter convolutions at the selected output word rate. All configurations work for a maxi-
mum digital filter clock, but lower clock rates consume less power.
Standby Mode
The CS5378 can be placed in a low-power standby mode by sending the ‘Filter Stop’ configuration com-
mand and programming the digital filter clock to 32 kHz. In this mode the digital filter idles, consuming
minimal power until re-enabled by later configuration commands.
Bits 23:20 19:16 15:12 11:8 7:4 3:0
Selection 0000 0000 IIR2 IIR1 FIR2 FIR1
Figure 22. FIR and IIR Coefficient Set Selection Word
Bits 15:12 IIR2 Coefficients
0000 3 Hz @ 2000 SPS
0001 3 Hz @ 1000 SPS
0010 3 Hz @ 500 SPS
0011 3 Hz @ 333 SPS
0100 3 Hz @ 250 SPS
Bits 11:8 IIR1 Coefficients
0000 3 Hz @ 2000 SPS
0001 3 Hz @ 1000 SPS
0010 3 Hz @ 500 SPS
0011 3 Hz @ 333 SPS
0100 3 Hz @ 250 SPS
Bits 7:4 FIR2 Coefficients
0000 Linear Phase
0001 Minimum Phase
Bits 3:0 FIR1 Coefficients
0000 Linear Phase
0001 Minimum Phase