Bosch TTCAN - Manual (Page 22)

User’s Manual
BOSCH - 22/77 -
Revision 1.6 TTCAN
11.11.02
manual_about.fm
ClrIntPnd Clear Interrupt Pending Bit
Note : When writing to a Message Object, this bit is ignored.
TxRqst/NewDatAccess Transmission Request Bit
one set TxRqst bit
zero TxRqst bit unchanged
Note : If a transmission is requested by setting TxRqst/NewDat in the IFx Command Mask Register,
bit TxRqst in the IFx Message Control Register will be ignored.
Data A Access Data Bytes 0-3
one
transfer Data Bytes 0-3 to Message Object.
zero Data Bytes 0-3 unchanged.
Data B Access Data Bytes 4-7
one
transfer Data Bytes 4-7 to Message Object.
zero Data Bytes 4-7 unchanged.
3.3.1.2 Direction = Read
Mask Access Mask Bits
one
transfer Identifier Mask + MDir + MXtd to IFx Message Buffer Register.
zero Mask bits unchanged.
Arb Access Arbitration Bits
one
transfer Identifier + Dir + Xtd + MsgVal to IFx Message Buffer Register.
zero Arbitration bits unchanged.
Control Access Control Bits
one
transfer Control Bits to IFx Message Buffer Register.
zero Control Bits unchanged.
ClrIntPnd Clear Interrupt Pending Bit
one clear IntPnd bit in the Message Object.
zero IntPnd bit remains unchanged.
TxRqst/NewDatAccess New Data Bit
one clear NewDat bit in the Message Object.
zero NewDat bit remains unchanged.
Note : A read access to a Message Object can be combined with the reset of the control bits IntPnd
and NewDat. The values of these bits transferred to the IFx Message Control Register always
reflect the status before resetting them.
Data A Access Data Bytes 0-3
one
transfer Data Bytes 0-3 to IFx Message Buffer Register.
zero Data Bytes 0-3 unchanged.
Data B Access Data Bytes 4-7
one
transfer Data Bytes 4-7 to IFx Message Buffer Register.
zero Data Bytes 4-7 unchanged.
Note : The speed of the message transfer does not depend on how many bytes are transferred.
3.3.2 IFx Command Request Registers
A message transfer is started as soon as the CPU has written the message number to low
byte of the Command Request Register. With this write operation, the Busy bit is
automatically set to ‘1’ to notify the CPU that a transfer is in progress. After a wait time of 3 to