Bosch TTCAN - Manual (Page 76)

User’s Manual
BOSCH - 76/77 -
Revision 1.6 TTCAN
11.11.02
manual_about.fm
6.2 Timing of the WAIT output signal
If the Customer Interfaces is implemented with a wait-function, the CPU is halted while a
message transfer is in progress between the IFx Registers and the Message RAM, when the
module’s optional output port CAN_WAIT_B is at active low level. Figure 22 shows the timing
of CAN_WAIT_B with respect to the modules internal clock CAN_CLK. The number of clock
cycles needed for a transfer between the IFx Registers and the Message RAM can vary
between 3 and 6 clock cycles depending on the state of the Message Handler (idle,
acceptance filtering, load / store CAN message,
…
).
Figure 22: Timing of WAIT output signal CAN_WAIT_B.
The message transfer is also shown by the Busy bit in the high byte of the Command Request
Register. The Busy bit is automatically set to ‘1’ by the command write operation to notify the
CPU that a transfer is in progress. After a time of 3 to 6 CAN_CLK periods, the transfer
between the Interface Register and the Message RAM has completed and the Busy bit is
cleared to ‘0’. This time is at the upper limit when the message transfer coincides with a CAN
message transmission start, acceptance filtering, or message storage. An IFx Register cannot
be read or written while its Busy bit is set, but other registers may be accessed in that time.
The waiting time is not dependent on the amount of data being transferred.
6.3 Interrupt Timing
Figure 23 shows the timing at the modules interrupt port CAN_INT (active low) with respect to
the modules internal clock CAN_CLK.
Figure 23: Timing of interrupt signal CAN_INT.
If several interrupt flags of the TTCAN module are set (status interrupt, message interrupts),
all interrupt flags have to be reset before the CAN_INT returns to passive level.
3 - 6 CAN_CLK Cycles
CAN_CLK
CAN_WAIT_B
Write Message-No. to IFx
Command Request Register =>
Busy = ‘1’
Requested Data loaded
into / from IFx Registers =>
Busy = ‘0’
CAN_CLK
CAN_INT
Enabled Interrupt Flag set
while IE = ‘1’
Reset Interrupt Flag
or write IE = ‘0’