Document Outline

• 1. About this Document
  • 1.1 Change Control
    • 1.1.1 Current Status
    • 1.1.2 Change History
  • 1.2 Conventions
  • 1.3 Scope
  • 1.4 References
  • 1.5 Terms and Abbreviations
• 2. Functional Description
  • 2.1 Functional Overview
  • 2.2 Block Diagram
  • 2.3 Operating Modes
    • 2.3.1 Software Initialisation
    • 2.3.2 CAN Message Transfer
    • 2.3.3 Disabled Automatic Retransmission
    • 2.3.4 Test Mode
      • 2.3.4.1 Test Register (addresses 0x0B & 0x0A)
      • 2.3.4.2 Disable Watchdog Mode
      • 2.3.4.3 Silent Mode
      • 2.3.4.4 Loop Back Mode
      • 2.3.4.5 Loop Back combined with Silent Mode
      • 2.3.4.6 Software control of Pin CAN_TX
      • 2.3.4.7 No Message RAM Mode
• 3. Programmer’s Model
  • 3.1 Hardware Reset Description
  • 3.2 CAN Protocol Related Registers
    • 3.2.1 CAN Control Register (addresses 0x01 & 0x00)
    • 3.2.2 Status Register (addresses 0x03 & 0x02)
      • 3.2.2.1 Status Interrupts
    • 3.2.3 Error Counter (addresses 0x05 & 0x04)
    • 3.2.4 Bit Timing Register (addresses 0x07 & 0x06)
    • 3.2.5 BRP Extension Register (addresses 0x0D & 0x0C)
  • 3.3 Message Interface Register Sets
    • 3.3.1 IFx Command Mask Registers
      • 3.3.1.1 Direction = Write
      • 3.3.1.2 Direction = Read
    • 3.3.2 IFx Command Request Registers
    • 3.3.3 IFx Message Buffer Registers
      • 3.3.3.1 IFx Mask Registers
      • 3.3.3.2 IFx Arbitration Registers
      • 3.3.3.3 IFx Message Control Registers
      • 3.3.3.4 IFx Data A and Data B Registers
    • 3.3.4 Message Object in the Message Memory
  • 3.4 Message Handler Registers
    • 3.4.1 Interrupt Register (addresses 0x09 & 0x08)
    • 3.4.2 Transmission Request Registers
    • 3.4.3 New Data Registers
    • 3.4.4 Interrupt Pending Registers
    • 3.4.5 Message Valid 1 Register
  • 3.5 Registers for Time Triggered Communication
    • 3.5.1 Trigger Memory Access Register (addresses 0x0F & 0x0E)
    • 3.5.2 IF1 Data B1 and B2 Registers for Trigger Memory Access
    • 3.5.3 TT Operation Mode Register (addresses 0x29 & 0x28)
    • 3.5.4 TT Matrix Limits1 Register (addresses 0x2B & 0x2A)
    • 3.5.5 TT Matrix Limits2 Register (addresses 0x2D & 0x2C)
    • 3.5.6 TT Application Watchdog Limit Register (addresses 0x2F & 0x2E)
    • 3.5.7 TT Interrupt Enable Register (addresses 0x31 & 0x30)
    • 3.5.8 TT Interrupt Vector Register (addresses 0x33 & 0x32)
    • 3.5.9 TT Global Time Register (addresses 0x35 & 0x34)
    • 3.5.10 TT Cycle Time Register (addresses 0x37 & 0x36)
    • 3.5.11 TT Local Time Register (addresses 0x39 & 0x38)
    • 3.5.12 TT Master State Register (addresses 0x3B & 0x3A)
    • 3.5.13 TT Cycle Count Register (addresses 0x3D & 0x3C)
    • 3.5.14 TT Error Level Register (addresses 0x3F & 0x3E)
    • 3.5.15 TUR Numerator Configuration Low Register (addresses 0x57 & 0x56)
    • 3.5.16 TUR Denominator Configuration Register (addresses 0x59 & 0x58)
    • 3.5.17 TUR Numerator Actual Registers (addresses 0x5B & 0x5A)
    • 3.5.18 TT Stop_Watch Register (addresses 0x61 & 0x60)
    • 3.5.19 TT Global Time Preset Register (addresses 0x65 & 0x64)
    • 3.5.20 TT Clock Control Register (addresses 0x67 & 0x66)
    • 3.5.21 TT Sync_Mark Register (addresses 0x69 & 0x68)
    • 3.5.22 TT Time Mark Register (addresses 0x6D & 0x6C)
    • 3.5.23 TT Gap Control Register (addresses 0x6F & 0x6E)
• 4. CAN Application
  • 4.1 Internal CAN Message Handling
    • 4.1.1 Data Transfer Between IFx Registers and Message RAM
    • 4.1.2 Transmission of Messages in Event Driven CAN Communication
    • 4.1.3 Acceptance Filtering of Received Messages
      • 4.1.3.1 Reception of Data Frame
      • 4.1.3.2 Reception of Remote Frame
    • 4.1.4 Storing Received Messages in FIFO Buffers
    • 4.1.5 Receive / Transmit Priority
  • 4.2 Configuration of the Module
    • 4.2.1 Configuration of the Bit Timing
      • 4.2.1.1 Bit Time and Bit Rate
      • 4.2.1.2 Propagation Time Segment
      • 4.2.1.3 Phase Buffer Segments and Synchronisation
      • 4.2.1.4 Oscillator Tolerance Range
      • 4.2.1.5 Configuration of the CAN Protocol Controller
      • 4.2.1.6 Calculation of the Bit Timing Parameters
      • 4.2.1.7 Example for Bit Timing at high Baudrate
      • 4.2.1.8 Example for Bit Timing at low Baudrate
    • 4.2.2 Configuration of the Message Memory
      • 4.2.2.1 Configuration of a Transmit Object for Data Frames
      • 4.2.2.2 Configuration of a Single Receive Object for Data Frames
      • 4.2.2.3 Configuration of a FIFO Buffer
      • 4.2.2.4 Configuration of a Single Receive Object for Remote Frames
  • 4.3 CAN Communication
    • 4.3.1 Handling of Interrupts
    • 4.3.2 Updating a Transmit Object
    • 4.3.3 Changing a Transmit Object
    • 4.3.4 Reading Received Messages
    • 4.3.5 Requesting New Data for a Receive Object
    • 4.3.6 Reading from a FIFO Buffer
• 5. TTCAN Application
  • 5.1 TTCAN Configuration
    • 5.1.1 TTCAN Timing
    • 5.1.2 Message Scheduling
    • 5.1.3 Trigger Memory
    • 5.1.4 Message Objects
      • 5.1.4.1 Reference Message
      • 5.1.4.2 Periodic Transmit Message
      • 5.1.4.3 Event Driven Transmit Message
  • 5.2 TTCAN Schedule Initialisation
    • 5.2.1 Time Slaves
    • 5.2.2 Potential Time Masters
  • 5.3 TTCAN Message Handling
    • 5.3.1 Message Reception
    • 5.3.2 Message Transmission
      • 5.3.2.1 Periodic Messages
      • 5.3.2.2 Event Driven Messages
  • 5.4 TTCAN Gap Control
  • 5.5 Stopwatch
  • 5.6 Local Time, Cycle Time, and Global Time and External Clock Synchronisation
  • 5.7 TTCAN Interrupt and Error Handling
  • 5.8 Configuration Example
• 6. CPU Interface
  • 6.1 Customer Interface
  • 6.2 Timing of the WAIT output signal
  • 6.3 Interrupt Timing
• 7. Appendix
  • 7.1 List of Figures