Kontron KTH81-mITX - Manual (Page 64)

KTD-N0882-H Page 64 Slot Connectors
KTQ87/KTH81 Users Guide
ARBITRATION PINS (BUS MASTERS ONLY)
REQ#
Request indicates to the arbiter that this agent desires use of the bus. This is a point to point signal. Every master
has its own REQ# which must be tri-stated while RST# is asserted.
GNT# Grant indicates to the agent that access to the bus has been granted. This is a point to point signal. Every master
has its own GNT# which must be ignored while RST# is asserted.
While RST# is asserted, the arbiter must ignore all REQ# lines since they are tri-stated and do not contain a valid
request. The arbiter can only perform arbitration after RST# is deasserted. A master must ignore its GNT# while
RST# is asserted. REQ# and GNT# are tri-state signals due to power sequencing requirements when 3.3V or 5.0V
only add-in boards are used with add-in boards that use a universal I/O buffer.
ERROR REPORTING PINS.
The error reporting pins are required by all devices and maybe asserted when enabled
PERR# Parity Error is only for the reporting of data parity errors during all PCI transactions except a Special Cycle. The
PERR# pin is sustained tri-state and must be driven active by the agent receiving data two clocks following the data
when a data parity error is detected. The minimum duration of PERR# is one clock for each data phase that a data
parity error is detected. (If sequential data phases each have a data parity error, the PERR# signal will be asserted
for more than a single clock.) PERR# must be driven high for one clock before being tri-stated as with all sustained
tri-state signals. There are no special conditions when a data parity error may be lost or when reporting of an error
may be delayed. An agent cannot report a PERR# until it has claimed the access by asserting DEVSEL# (for a target)
and completed a data phase or is the master of the current transaction.
SERR# System Error is for reporting address parity errors, data parity errors on the Special Cycle command, or any other
system error where the result will be catastrophic. If an agent does not want a non-maskable interrupt (NMI) to be
generated, a different reporting mechanism is required. SERR# is pure open drain and is actively driven for a single
PCI clock by the agent reporting the error. The assertion of SERR# is synchronous to the clock and meets the setup
and hold times of all bused signals. However, the restoring of SERR# to the deasserted state is accomplished by a
weak pullup (same value as used for s/t/s) which is provided by the system designer and not by the 64signaling
agent or central resource. This pull-up may take two to three clock periods to fully restore SERR#. The agent that
reports SERR#s to the operating system does so anytime SERR# is sampled asserted.
INTERRUPT PINS (OPTIONAL).
Interrupts on PCI are optional and defined as “level sensitive,” asserted low (negative true), using open drain output drivers. The
assertion and deassertion of INTx# is asynchronous to CLK. A device asserts its INTx# line when requesting attention from its device
driver. Once the INTx# signal is asserted, it remains asserted until the device driver clears the pending request. When the request is
cleared, the device deasserts its INTx# signal. PCI defines one interrupt line for a single function device and up to four interrupt
lines for a multi-function device or connector. For a single function device, only INTA# may be used while the other three interrupt
lines have no meaning.
INTA# Interrupt A is used to request an interrupt.
INTB# Interrupt B is used to request an interrupt and only has meaning on a multi-function device.
INTC# Interrupt C is used to request an interrupt and only has meaning on a multi-function device.
INTD# Interrupt D is used to request an interrupt and only has meaning on a multi-function device.
KTQ81/Flex & KTH81/Flex PCI IRQ & INT routing
REQ GNT IDSEL INTA INTB INTC INTD
REQ0 GNT0 17 INTA INTB INTC INTD