Kontron CP305 - Manual (Page 9)

CP305 Preface
ID 1035-7168, Rev. 2.0 Page ix
P R E L I M I N A R Y
List of Tables
1-1 System Relevant Information .................................................................... 1 - 5
1-2 CP305 4HP Version Main Specifications ................................................... 1 - 9
1-3 Standards ................................................................................................ 1 - 14
1-4 Additional Standards for Boards with Ruggedized Service ..................... 1 - 15
1-5 Add. Stand. for Boards with Ruggedized Service and Conformal Coating 1 - 15
1-6 Related Publications ............................................................................... 1 - 16
2-1 Processors Supported on the CP305 ........................................................ 2 - 3
2-2 Supported Memory Configurations ............................................................ 2 - 4
2-3 SMBus Device Addresses ......................................................................... 2 - 6
2-4 EEPROM Address Map ............................................................................. 2 - 7
2-5 CompactFlash Connector Pinout ............................................................... 2 - 8
2-6 POST Code Indication ............................................................................... 2 - 9
2-7 USB Connectors J9 and J10 Pinout ........................................................ 2 - 10
2-8 D-Sub VGA Connector J6 Pinout ............................................................ 2 - 11
2-9 Pinout of the Dual GbE Con. J11A/B ....................................................... 2 - 12
2-10 SATA Port Mapping ................................................................................. 2 - 13
2-11 SATA Connector J4 Pinout ...................................................................... 2 - 13
2-12 CompactPCI Bus Connector J1 Pinout ................................................... 2 - 15
2-13 64-bit CompactPCI Bus Connector J2 Pinout (CP305 Front I/O Vers.)... 2 - 16
2-14 Rear I/O CompactPCI Bus Connector J2 Pinout (CP305 Rear I/O Vers.) 2 - 18
2-15 GPIO Signal Description ......................................................................... 2 - 19
4-1 Clearing BIOS CMOS Setup ..................................................................... 4 - 3
4-2 I/O Address Map ........................................................................................ 4 - 3
4-3 Watchdog Timer Control Register ............................................................. 4 - 5
4-4 Hardware and Logic Revision Index Register ........................................... 4 - 6
4-5 Reset Status Register ................................................................................ 4 - 7
4-6 I/O Status Register .................................................................................... 4 - 8
4-7 I/O Configuration Register ......................................................................... 4 - 9
4-8 Board ID Register .................................................................................... 4 - 10
4-9 Board Interrupt Configuration Register .................................................... 4 - 11
4-10 BIOS Configuration Register ................................................................... 4 - 12
4-11 LED Control Register ............................................................................... 4 - 13