Maxim Integrated High-Speed Microcontroller Users Guide: DS80C390 Supplement User Manual
Maxim Integrated Hardware
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This document is provided as a supplement to the High-Speed Microcontroller User’s Guide, covering new or
modified features specific to the DS80C390. This document must be used in conjunction with Dallas
Semiconductor’s High-Speed Microcontroller User’s Guide. Addenda are arranged by the section numbers
that correspond to sections in the High-Speed Microcontroller User’s Guide.
The following additions and changes, with respect to the High-Speed Microcontroller User’s Guide, are contained in
this document. This document is a work in progress, and updates/additions are added when available.
TABLE OF CONTENTS
0 (C0RMS0).................................................................................... 26
1 (C0RMS1).................................................................................... 27
0 (C0TMA0) ............................................................... 32
1 (C0TMA1) ............................................................... 33
High-Speed Microcontroller User’s Guide:
DS80C390 Supplement
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Table of contents
Document Outline
- TABLE OF CONTENTS
- ADDENDUM TO SECTION 2: ORDERING INFORMATION
- ADDENDUM TO SECTION 4: PROGRAMMING MODEL
- MEMORY MAP
- REGISTER MAP
- BIT ADDRESSABLE LOCATIONS
- WORKING REGISTERS
- STACK
- SPECIAL FUNCTION REGISTERS
- PORT 4 (P4)
- STACK POINTER (SP)
- DATA POINTER LOW 0 (DPL)
- DATA POINTER HIGH 0 (DPH)
- DATA POINTER LOW 1 (DPL1)
- DATA POINTER HIGH 1 (DPH1)
- DATA POINTER SELECT (DPS)
- POWER CONTROL (PCON)
- TIMER/COUNTER CONTROL (TCON)
- TIMER MODE CONTROL (TMOD)
- TIMER 0 LSB (TL0)
- TIMER 1 LSB (TL1)
- TIMER 0 MSB (TH0)
- TIMER 1 MSB (TH1)
- CLOCK CONTROL (CKCON)
- PORT 1 (P1)
- EXTERNAL INTERRUPT FLAG (EXIF)
- PORT 4 CONTROL REGISTER (P4CNT)
- DATA POINTER EXTENDED REGISTER 0 (DPX)
- DATA POINTER EXTENDED REGISTER 1 (DPX1)
- CAN 0 RECEIVE MESSAGE STORED REGISTER 0 (C0RMS0)
- CAN 0 RECEIVE MESSAGE STORED REGISTER 1 (C0RMS1)
- SERIAL PORT 0 CONTROL (SCON0)
- SERIAL DATA BUFFER 0 (SBUF0)
- REVISION ID REGISTER (RID)
- EXTENDED STACK POINTER REGISTER (ESP)
- ADDRESS PAGE REGISTER (AP)
- ADDRESS CONTROL REGISTER (ACON)
- CAN 0 TRANSMIT MESSAGE ACKNOWLEDGEMENT REGISTER 0 (C0TMA0)
- CAN 0 TRANSMIT MESSAGE ACKNOWLEDGEMENT REGISTER 1 (C0TMA1)
- PORT 2 (P2)
- PORT 5 (P5)
- PORT 5 CONTROL REGISTER (P5CNT)
- CAN 0 CONTROL REGISTER (C0C)
- CAN 0 STATUS REGISTER (C0S)
- CAN 0 INTERRUPT REGISTER (C0IR)
- CAN 0 TRANSMIT ERROR REGISTER (C0TE)
- CAN 0 RECEIVE ERROR REGISTER (C0RE)
- INTERRUPT ENABLE (IE)
- SLAVE ADDRESS REGISTER 0 (SADDR0)
- SLAVE ADDRESS REGISTER 1 (SADDR1)
- CAN 0 MESSAGE CENTER 1 CONTROL REGISTER (C0M1C)
- CAN 0 MESSAGE CENTER 2 CONTROL REGISTER (C0M2C)
- CAN 0 MESSAGE CENTER 3 CONTROL REGISTER (C0M3C)
- CAN 0 MESSAGE CENTER 4 CONTROL REGISTER (C0M4C)
- CAN 0 MESSAGE CENTER 5 CONTROL REGISTER (C0M5C)
- PORT 3 (P3)
- CAN 0 MESSAGE CENTER 6 CONTROL REGISTER (C0M6C)
- CAN 0 MESSAGE CENTER 7 CONTROL REGISTER (C0M7C)
- CAN 0 MESSAGE CENTER 8 CONTROL REGISTER (C0M8C)
- CAN 0 MESSAGE CENTER 9 CONTROL REGISTER (C0M9C)
- CAN 0 MESSAGE CENTER 10 CONTROL REGISTER (C0M10C)
- INTERRUPT PRIORITY (IP)
- SLAVE ADDRESS MASK ENABLE REGISTER 0 (SADEN0)
- SLAVE ADDRESS MASK ENABLE REGISTER 1 (SADEN1)
- CAN 0 MESSAGE CENTER 11 CONTROL REGISTER (C0M11C)
- CAN 0 MESSAGE CENTER 12 CONTROL REGISTER (C0M12C)
- CAN 0 MESSAGE CENTER 13 CONTROL REGISTER (C0M13C)
- CAN 0 MESSAGE CENTER 14 CONTROL REGISTER (C0M14C)
- CAN 0 MESSAGE CENTER 15 CONTROL REGISTER (C0M15C)
- SERIAL PORT CONTROL (SCON1)
- SERIAL DATA BUFFER 1 (SBUF1)
- POWER MANAGEMENT REGISTER (PMR)
- STATUS REGISTER (STATUS)
- MEMORY CONTROL REGISTER (MCON)
- TIMED ACCESS REGISTER (TA)
- TIMER 2 CONTROL (T2CON)
- TIMER 2 MODE (T2MOD)
- TIMER 2 CAPTURE LSB (RCAP2L)
- TIMER 2 CAPTURE MSB (RCAP2H)
- TIMER 2 LSB (TL2)
- TIMER 2 MSB (TH2)
- CLOCK OUTPUT REGISTER (COR)
- PROGRAM STATUS WORD (PSW)
- MULTIPLIER CONTROL REGISTER ZERO (MCNT0)
- MULTIPLIER CONTROL REGISTER ONE (MCNT1)
- MULTIPLIER A REGISTER (MA)
- MULTIPLIER B REGISTER (B)
- MULTIPLIER C REGISTER (C)
- CAN 1 RECEIVE MESSAGE STORED REGISTER 0 (C1RMS0)
- CAN 1 RECEIVE MESSAGE STORED REGISTER 1 (C1RMS1)
- WATCHDOG CONTROL (WDCON)
- CAN 1 TRANSMIT MESSAGE ACKNOWLEDGEMENT REGISTER 0 (C1TMA0)
- CAN 1 TRANSMIT MESSAGE ACKNOWLEDGEMENT REGISTER 1 (C1TMA1)
- ACCUMULATOR (A or ACC)
- CAN 1 CONTROL REGISTER (C1C)
- CAN 1 STATUS REGISTER (C1S)
- CAN 1 INTERRUPT REGISTER (C1IR)
- CAN 1 TRANSMIT ERROR REGISTER (C1TE)
- CAN 1 RECEIVE ERROR REGISTER (C1RE)
- EXTENDED INTERRUPT ENABLE (EIE)
- MOVX EXTENDED ADDRESS REGISTER (MXAX)
- CAN 1 MESSAGE CENTER 1 CONTROL REGISTER (C1M1C)
- CAN 1 MESSAGE CENTER 2 CONTROL REGISTER (C1M2C)
- CAN 1 MESSAGE CENTER 3 CONTROL REGISTER (C1M3C)
- CAN 1 MESSAGE CENTER 4 CONTROL REGISTER (C1M4C)
- CAN 1 MESSAGE CENTER 5 CONTROL REGISTER (C1M5C)
- B REGISTER (B)
- CAN 1 MESSAGE CENTER 6 CONTROL REGISTER (C1M6C)
- CAN 1 MESSAGE CENTER 7 CONTROL REGISTER (C1M7C)
- CAN 1 MESSAGE CENTER 8 CONTROL REGISTER (C1M8C)
- CAN 1 MESSAGE CENTER 9 CONTROL REGISTER (C1M9C)
- CAN 1 MESSAGE CENTER 10 CONTROL REGISTER (C1M10C)
- EXTENDED INTERRUPT PRIORITY (EIP)
- CAN 1 MESSAGE CENTER 11 CONTROL REGISTER (C1M11C)
- CAN 1 MESSAGE CENTER 12 CONTROL REGISTER (C1M12C)
- CAN 1 MESSAGE CENTER 13 CONTROL REGISTER (C1M13C)
- CAN 1 MESSAGE CENTER 14 CONTROL REGISTER (C1M14C)
- CAN 1 MESSAGE CENTER 15 CONTROL REGISTER (C1M14C)
- ADDENDUM TO SECTION 5: CPU TIMING
- ADDENDUM TO SECTION 6: MEMORY ACCESS
- ADDENDUM TO SECTION 7: POWER MANAGEMENT
- ADDENDUM TO SECTION 8: RESET CONDITIONS
- ADDENDUM TO SECTION 10: PARALLEL I/O
- ADDENDUM TO SECTION 11: PROGRAMMABLE TIMERS
- ADDENDUM TO SECTION 12: SERIAL I/O
- ADDENDUM TO SECTION 13: TIMED ACCESS PROTECTION
- ADDENDUM TO SECTION 16: INSTRUCTION SET DETAILS
- SECTION 19: CONTROLLER AREA NETWORK (CAN) MODULE
- MOVX MESSAGE CENTERS FOR CAN 0
- MOVX MESSAGE CENTERS FOR CAN 1
- CAN MOVX REGISTER DESCRIPTION
- CAN Media ID Mask Register 0 (CnMID0)
- CAN Media ID Mask Register 1 (CnMID1)
- CAN Media Arbitration Register 0 (CnMA0)
- CAN Media Arbitration Register 1 (CnMA1)
- CAN Bus Timing Register 0 (CnBT0)
- CAN Bus Timing Register 1 (CnBT1)
- CAN Standard Global Mask Register 0 (CnSGM0)
- CAN Standard Global Mask Register 1 (CnSGM1)
- CAN Extended Global Mask Register 0 (CnEGM0)
- CAN Extended Global Mask Register 1 (CnEGM1)
- CAN Extended Global Mask Register 2 (CnEGM2)
- CAN Extended Global Mask Register 3 (CnEGM3)
- CAN Message Center 15 Mask Register 0 (CnM15M0)
- CAN Message Center 15 Mask Register 1 (CnM15M1)
- CAN 0 Message Center 15 Mask Register 2 (CnM15M2)
- CAN 0 Message Center 15 Mask Register 3 (CnM15M3)
- CAN MESSAGE CENTER MOVX REGISTER DESCRIPTIONS
- CAN Message Center y Arbitration Register 0 (CnMyAR0)
- CAN Message Center y Arbitration Register 1 (CnMyAR1)
- CAN Message Center y Arbitration Register 2 (CnMyAR2)
- CAN Message Center y Arbitration Register 3 (CnMyAR3)
- CAN Message Center y Format Register (CnMyF)
- CAN Message Center y Data Byte 0 (CnMyD0)
- CAN Message Center y Data Byte 1 (CnMyD1)
- CAN Message Center y Data Byte 2 (CnMyD2)
- CAN Message Center y Data Byte 3 (CnMyD3)
- CAN Message Center y Data Byte 4 (CnMyD4)
- CAN Message Center y Data Byte 5 (CnMyD5)
- CAN Message Center y Data Byte 6 (CnMyD6)
- CAN Message Center y Data Byte 7 (CnMyD7)
- FRAME TYPES
- Data Frame
- Start of Frame (SOF) (Standard and Extended Format)
- Arbitration Field (Standard and Extended Format)
- Control Field: (Standard and Extended Format)
- Data Field (Standard and Extended Format)
- CRC Field (Standard and Extended Format)
- Acknowledge Field (ACK): (Standard and Extended Format)
- End of Frame (Standard and Extended Format)
- Interframe Spacing (Intermission): (Standard and Extended Format)
- Remote Frame (Standard and Extended Format)
- Error Frame
- Overload Frame
- Data Frame
- INITIALIZING THE CAN CONTROLLERS
- CAN INTERRUPTS
- ARBITRATION/MASKING CONSIDERATIONS
- MESSAGE CENTER 15
- TRANSMITTING AND RECEIVING MESSAGES
- REMOTE FRAME HANDLING IN RELATION TO THE DTBYC BITS
- OVERWRITE ENABLE/DISABLE FEATURE
- USING THE AUTOBAUD FEATURE
- BUS OFF/BUS OFF RECOVERY AND ERROR COUNTER OPERATION
- BIT TIMING
- SECTION 20: ARITHMETIC ACCELERATOR