Maxim Integrated High-Speed Microcontroller Users Guide: DS80C390 Supplement - Manual (Page 40)

High-Speed Microcontroller User’s Guide: DS80C390 Supplement
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RXS
Bit 4 CAN 0 Receive Status. This bit indicates whether or not messages have been
received since the last read of the CAN 0 Status Register. RXS is only set by the
CAN 0 logic and must be cleared by the Microcontroller software, the CRST bit,
or a system Reset.
1 = The meaning of RXS=1 is dependent on the Autobaud bit, AUTOB.
AUTOB=0, RXS = 1 indicates that a message has been both successfully
received and stored in one of the message centers by CAN 0 since the last
read of the CAN 0 Status Register.
AUTOB=1, RXS = 1 indicates that a message has been successfully received
by CAN 0 since the last read of the CAN 0 Status Register. Note that
messages that are successfully received without errors but do not pass the
arbitration filtering will still set the RXS bit.
0 = No messages have been successfully received since the last read of the CAN 0
Status Register.
When STIE= 1 and the RXS bit transitions from 0 to 1, the CAN Interrupt
Register (C0IR;A5h) will change to 01h to indicate a pending interrupt due to a
change in the CAN Status Register(C0S;A4h). Reading any bit in the C0S register
will clear the pending interrupt, causing the C0IR register to change to 00h if no
interrupts are pending or the appropriate value if a lower priority message center
interrupt is pending. If a second successful reception is detected prior to or after
the clearing of the RXS bit in the Status Register, a second status change interrupt
flag will be set, issuing a second interrupt. Each new successful reception will
generate an interrupt request independent of the previous state of the RXS bit, as
long as the CAN Status Register has been read to clear the previous status change
interrupt flag. Note that if software changes RXS from 0 to 1, an artificial Status
Change Interrupt (STIE=1) will be generated. Thus, if RXS was previously set to
0 and a reception was successful, RXS will be set to 1 and an enabled interrupt
may be asserted. An interrupt may be asserted (if enabled) if software changes
RXS from 0 to 1. If RXS was previously set to 1 and a reception was successful,
RXS remains set and an interrupt may be asserted if enabled. No interrupt will be
asserted if software attempts to set RXS=1 while the bit is already set.
TXS
Bit 3 CAN 0 Transmit Status. This bit indicates whether or not one or more messages
have been successfully transmitted since the last read of the CAN 0 Status
Register. TXS is only set by the CAN 0 logic and is not cleared by the CAN
controller but is only cleared by software, the CRST bit, or a system Reset.
1 = A message has been successfully transmitted by CAN 0 (error free and
acknowledged) since the last read of the CAN 0 Status Register.
0 = No messages have been successfully transmitted since the last read of the
CAN 0 Status Register.
When STIE= 1 and the TXS bit transitions from 0 to 1, the CAN Interrupt
Register (C0IR;A5h) will change to 01h to indicate a pending interrupt due to a
change in the CAN Status Register. Reading any bit in the C0S register will clear
the pending interrupt, causing C0IR to change to 00h if no interrupts are pending
or the appropriate value if a lower priority message center interrupt is pending. If
a second successful transmission is detected prior to or after the clearing of the