CyberResearch PCIDIO 48H - Manual (Page 35)

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• Operation Theorem
The 8254 timer/ counter IC occupies 4 I/O address. Users can refer to
Tundra's or Intel's data sheet for a full description of the 8254 features. You
can download the 8254 data sheet from the following web site:
http://support.intel.com/support/controllers/peripheral/231164.htm
or
http://www.tundra.com (for Tundra’s 82C54 datasheet.)
4.2.2 Cascaded 32 Bits Timer
The input clock frequency of the cascaded timers is 2MHz. The output of the
timer is send to the interrupt circuit (refer to section 4.3). Therefore, the
maximum and minimum watchdog timer interrupt frequency is
(2MHz)/(2*2)=500KHz and (2MHz)/(65535*65535)= 0.000466Hz
respectively.
4.2.3 Event Counter and Edge Control
The counter #0 of the 8254 chip can be used as an event counter. The
input of counter #0 is PC4 of CN1 (P1C4). The counter clock trigger
direction (H to L or L to H) is programmable. The gate control is always
enabled. The output is send to interrupt system which named as event IRQ.
If counter #0 is set as 8254 mode 0, the event counter IRQ will generate
when the counter value is counting down to zero.
4.3 Interrupt Multiplexing
4.3.1 Architecture
The 48H/96H series products have a powerful and flexible interrupt
multiplexing circuit which is suitable for many applications. The board
could accept Dual Interrupts. The dual interrupt means that the hardware
can generate two interrupt request signals at the same time and the
software can service these two request signals by ISR. Note that th e dual
interrupts do not mean that the card occupies two IRQ levels.
The two interrupt request signals (INT1 and INT2) comes from digital input
signals or the timer/counter output. An interrupt source multiplexer (MUX) is
used to select the IRQ sources. Fig 4.3 shows the interrupt system.