Cypress CY62148EV30 - Manual

MoBL
®
CY62148EV30
4-Mbit (512K x 8) Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose
,
CA 95134-1709 • 408-943-2600
Document #: 38-05576 Rev. *G Revised August 4, 2008
Features
■ Very high speed: 45 ns
❐ Wide voltage range: 2.20V to 3.60V
■ Temperature ranges
❐ Industrial: –40°C to +85°C
❐ Automotive-A: –40°C to +85°C
■ Pin compatible with CY62148DV30
■ Ultra low standby power
❐ Typical standby current: 1 μA
❐ Maximum standby current: 7 μA (Industrial)
■ Ultra low active power
❐ Typical active current: 2 mA at f = 1 MHz
■ Easy memory expansion with CE, and OE features
■ Automatic power down when deselected
■ CMOS for optimum speed and power
■ Available in Pb-free 36-ball VFBGA, 32-pin TSOP II and 32-pin
SOIC [1] packages
Functional Description
The CY62148EV30 [2] is a high performance CMOS static RAM
organized as 512K words by 8 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL
®
) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption. Placing the device into standby mode reduces
power consumption by more than 99 percent when deselected
(CE HIGH). The eight input and output pins (IO
0
through IO
7
) are
placed in a high impedance state when the device is deselected
(CE HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW and WE LOW).
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. Data on the eight IO pins (IO
0
through IO
7
) is
then written into the location specified on the address pins (A
0
through A
18
).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under
these conditions, the contents of the memory location specified
by the address pins appear on the IO pins.
Notes
1. SOIC package is available only in 55 ns speed bin.
2. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at
http://www.cypress.com .
Logic Block Diagram
A0
IO0
IO7
IO1
IO2
IO3
IO4
IO5
IO6
A1
A2
A3
A4
A5
A6
A7
A8
A9
SENSE AMPS
POWER
DOWN
CE
WE
OE
A
13
A
14
A
15
A
16
A
17
ROW DECODER
COLUMN DECODER
512K x 8
ARRAY
INPUT BUFFER
A10
A11
A12
A
18
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