ADLINK USB-2405 - Manual (Page 49)

Operation 39
USB-2405
re-trigger number are valid from 1 to the buffer size allocated in
kernel space. The process repeats until the specified amount of
re-trigger signals is detected.
3.4 Programmable Function I/O
The USB-2405 supports powerful programmable I/O function pro-
vided by an FPGA chip, configurable as static digital input/output,
32-bit frequency counters, pulse output, synchronization sample
clock IN, and trigger IN. These signals are single-ended and 3.3 V/
TTL-compliant.
3.4.1 Static Digital Input/Output
Programmable function I/O can be used as static digital inputs or
outputs, with I/O lines readable and writeable by software polling,
with sample and update rate fully controlled by software timing.
3.4.2 Frequency Counter
Calculates base clocks occurring within a period (rising edge to
rising edge or falling edge to falling edge) of the repetitive input
signal, which is then converted to frequency value. Counter polar-
ity can be adjusted to rising edge active or falling edge active, with
maximum frequency measurable of 4MHz.
3.4.3 Pulse Output
The GPIO can also simulate a pulse output. By setting a varying
amount of Pulse_initial_cnt and Pulse_length_cnt, varying pulse
frequencies and duty cycles can be obtained. The maximum out-
put frequency is 4MHz, as shown.
Pulse_initial_count=7 Pulse_length_count=8
Timebase
PWM OUT