Simulating altera ip cores in other eda tools – Altera Unique Chip ID User Manual
Page 9
6. To regenerate the new IP variation for the new target device, click Generate. When generation is complete,
click Close.
7. Click Finish to complete migration of the IP core. Click OK if you are prompted to overwrite IP core
files. The Device Family column displays the migrated device support. The migration process replaces
<my_ip>
.qip
with the <my_ip>
.qsys
top-level IP file in your project.
If migration does not replace <my_ip>
.qip
with <my_ip>
.qsys
, click Project > Add/Remove Files
in Project to replace the file in your project.
Note:
8. Review the latest parameters in the parameter editor or generated HDL for correctness. IP migration
may change ports, parameters, or functionality of the IP core. During migration, the IP core's HDL
generates into a library that is different from the original output location of the IP core. Update any
assignments that reference outdated locations. If your upgraded IP core is represented by a symbol in a
supporting Block Design File schematic, replace the symbol with the newly generated <my_ip>
.bsf
after
migration.
The migration process may change the IP variation interface, parameters, and functionality. This
may require you to change your design or to re-parameterize your variant after the Upgrade IP
Note:
Components dialog box indicates that migration is complete. The Description field identifies IP
cores that require design or parameter changes.
Related Information
Simulating Altera IP Cores in other EDA Tools
The Quartus II software supports RTL and gate-level design simulation of Altera IP cores in supported EDA
simulators. Simulation involves setting up your simulator working environment, compiling simulation
model libraries, and running your simulation.
You can use the functional simulation model and the testbench or example design generated with your IP
core for simulation. The functional simulation model and testbench files are generated in a project
subdirectory. This directory may also include scripts to compile and run the testbench. For a complete list
of models or libraries required to simulate your IP core, refer to the scripts generated with the testbench.
You can use the Quartus II NativeLink feature to automatically generate simulation files and scripts.
NativeLink launches your preferred simulator from within the Quartus II software.
Altera Corporation
Altera Unique Chip ID IP Core User Guide
9
Simulating Altera IP Cores in other EDA Tools
ug-altchipid
2014.09.02