Fft ip core functional description, Fixed transform ffts, Variable streaming ffts – Altera FFT MegaCore Function User Manual

Page 24: Fft ip core functional description -1, Fixed transform ffts -1, Variable streaming ffts -1

Advertising
background image

FFT IP Core Functional Description

3

2014.12.15

UG-FFT

Subscribe

Send Feedback

Fixed Transform FFTs

The buffered, burst, and streaming FFTs use a radix-4 decomposition, which divides the input sequence

recursively to form four-point sequences, requires only trivial multiplications in the four-point DFT.

Radix-4 gives the highest throughput decomposition, while requiring non-trivial complex multiplications

in the post-butterfly twiddle-factor rotations only. In cases where N is an odd power of two, the FFT

MegaCore automatically implements a radix-2 pass on the last pass to complete the transform.
To maintain a high signal-to-noise ratio throughout the transform computation, the fixed transform FFTs

use a block-floating-point architecture, which is a trade-off point between fixed-point and full-floating-

point architectures.

Related Information

Block Floating Point Scaling

Variable Streaming FFTs

The variable streaming FFTs use fixed-point data representation or the floating point representation.
If you select the fixed-point data representation, the FFT variation uses a radix 2

2

single delay feedback,

which is fully pipelined. If you select the floating point representation, the FFT variation uses a mixed

radix-4/2. For a length N transform, log

4

(N) stages are concatenated together. The radix 2

2

algorithm has

the same multiplicative complexity of a fully pipelined radix-4 FFT, but the butterfly unit retains a radix-2

FFT. The radix-4/2 algorithm combines radix-4 and radix-2 FFTs to achieve the computational advantage

of the radix-4 algorithm while supporting FFT computation with a wider range of transform lengths. The

butterfly units use the DIF decomposition.
Fixed point representation allows for natural word growth through the pipeline. The maximum growth of

each stage is 2 bits. After the complex multiplication the data is rounded down to the expanded data size

using convergent rounding. The overall bit growth is less than or equal to log

2

(N)+1.

The floating point internal data representation is single-precision floating-point (32-bit, IEEE 754

representation). Floating-point operations provide more precise computation results but are costly in

hardware resources. To reduce the amount of logic required for floating point operations, the variable

streaming FFT uses fused floating point kernels. The reduction in logic occurs by fusing together several

floating point operations and reducing the number of normalizations that need to occur.

©

2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are

trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as

trademarks or service marks are the property of their respective holders as described at

www.altera.com/common/legal.html

. Altera warrants performance

of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any

products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,

product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device

specifications before relying on any published information and before placing orders for products or services.

ISO

9001:2008

Registered

www.altera.com

101 Innovation Drive, San Jose, CA 95134

Advertising