Audio extract, Aes output module, Aes input module – Altera Serial Digital Interface (SDI) MegaCore Function User Manual

Page 115: Audio embed p0/p1, Video pattern generator p0/p1, Audio pattern generator, Ancillary data insertion p0/p1, Transceiver dynamic reconfiguration control logic

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Chapter 4: SDI Audio IP Cores

4–27

Design Example

February 2013

Altera Corporation

Serial Digital Interface (SDI) MegaCore Function

User Guide

Audio Extract

The Audio Extract MegaCore function extracts the embedded AES audio from the SDI
stream. The Audio Extract MegaCore function routes the extracted AES audio to the
AES output of the daughter card.

AES Output Module

The AES output module converts the aud_de, aud_ws, and aud_data signals to AES
signal. This module configures the extracted internal AES audio signal, aud_data,
without the biphase mark encoding. When this module interfaces with the Audio
Extract MegaCore function, it must use the same clock as the Audio Extract MegaCore
function.

AES Input Module

The AES input module converts the AES signal to aud_de, aud_ws, and aud_data
(internal AES) signals to interface with Audio Embed P1. When this module interfaces
with the Audio Embed MegaCore function, both must use the same clock.

Audio Embed P0/P1

The Audio Embed P0 embeds the AES audio generated by the Audio Pattern
Generator into the video stream, as a transmitting data, for the SDI transmitter P0.
The Audio Embed P1 embeds the AES audio from the external AES input into the
video stream for the SDI duplex.

Video Pattern Generator P0/P1

You can configure the internal video pattern generator to output an SD-SDI, HD-SDI,
3G-SDI Level A or 3G-SDI Level B colorbar pattern.

Audio Pattern Generator

You can configure the internal audio pattern generator to create an AES audio test
sample that comprises an increasing count. You configure the generator using the
48-kHz clock output from the Audio Embed MegaCore function.

Ancillary Data Insertion P0/P1

The Ancillary Data Insertion module inserts the ancillary data defined by SMPTE352
into the SDI video stream.

Transceiver Dynamic Reconfiguration Control Logic

The transceiver dynamic reconfiguration control logic block handles the
reconfiguration of the receiver in the SDI duplex.

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