Altera Serial Digital Interface (SDI) MegaCore Function User Manual
Page 74
3–44
Chapter 3: Functional Description
Signals
Serial Digital Interface (SDI) MegaCore Function
February 2013
Altera Corporation
User Guide
rx_AP
[1:0]
Output
This is an active picture interval timing signal. The receiver
aserts this signal when the active picture interval is active.
HD-SDI/SD-SDI: bit 1 unused; bit 0 rx_ap
Dual link: bit 1 link B unused; bit 0 link A rx_ap
3G-SDI Level A: bit 1 unused; bit 0 rx_ap
3G-SDI Level B: bit 1 link A rx_ap; bit 0 link B rx_ap
rxdata
[(20N – 1):0]
Output
Receiver parallel data. SD-SDI uses 9:0; HD-SDI uses 20N
– 1:0.
SD-SDI bits 19:10 unused; bits 9:0 Cb, Y, Cr, Y multiplex
HD-SDI bits 19:10 Y; bits 9:0 C
Dual link: bits 39:30 Y link B; bits 29:20 C link B;
bits 19:10 Y link A, bits 9:0 C link A
3G-SDI Level A: bits 19:10 Y; bits 9:0 C
3G-SDI Level B: bits 19:10 Cb, Y, Cr, Y multiplex (link A);
bits 9:0 Cb, Y, Cr, Y multiplex (link B)
rx_data_valid_out
[1:0]
Output
Data valid from the oversampling logic. Asserted to
indicate current data on rxdata is valid.
Bit 0 of this bus indicates valid data on rxdata. When
receiving SMPTE 425M-B signals in 3G-SDI or triple
standard, bit 1 indicates that data on rxdata is from
virtual link A; bit 0 indicates the data is from virtual link B.
Refer to
and
, and SMPTE425M-B
2006 3Gb/s Signal/Data Serial Interface – Source Image
Format Mapping.
rx_F
[1:0]
Output
This is a field bit timing signal. This signal indicates which
video field is currently active. For interlaced frame, 0
means first field (F0) while 1 means second field (F1). For
progressive frame, the value is always 0.
HD-SDI/SD: bit 1 unused; bit 0 rx_f
Dual link: bit 1 unused; bit 0 rx_f
3G-SDI Level A: bit 1:0 unused
3G-SDI Level B: bit 1:0 unused
rx_H
[1:0]
Output
This is a horizontal blanking interval timing signal. The
receiver asserts this signal when the horizontal blanking
interval is active.
HD-SDI/SD-SDI: bit 1 unused; bit 0 rx_h
Dual link: bit 1 unused; bit 0 rx_h
3G-SDI Level A: bit 1 unused; bit 0 rx_h
3G-SDI Level B: bit 1 link A rx_h; bit 0 link B rx_h
Table 3–16. Interface Signals (Part 4 of 5)
Signal
Width
Direction
Description