Altera Serial Digital Interface (SDI) MegaCore Function - Manual (Page 129)

Appendix A: Constraints A–7
Constraints for the SDI Soft Transceiver
February 2013 Altera Corporation Serial Digital Interface (SDI) MegaCore Function
User Guide
■ Hold—zero clocks from the 337.5-MHz clock to the 135-MHz clock
Use the set_min_delay command to specify an absolute minimum delay for a given
path.
set_min_delay -from [get_clocks {rx_sd_refclk_337}] -to [get_clocks
{rx_sd_refclk_135}] 0.000
Use the set_max_delay command to specify an absolute maximum delay for a given
path.
set_max_delay -from [get_clocks {rx_sd_refclk_337}] -to [get_clocks
{rx_sd_refclk_135}] 4.430
Minimize Timing Skew
You must minimize the timing skew among the paths from I/O pins to the four
sampling registers (sample_a[0], sample_b[0], sample_c[0], and sample_d[0]). To
minimize the timing skew, manually place the sampling registers close to each other
and to the serial input pin. Because these four registers are using four different clock
domains, place two of the four registers in one LAB and the other two in another LAB.
Furthermore, place the two chosen LABs within the same row regardless of the
placement of the serial input. Finally, do not place the four sampling registers at the
immediate rows or columns next to the I/O, but at the second row or column next to
the I/O bank. This location is because inter-LAB interconnects between I/O banks
and their immediate rows or columns are much faster than core interconnect.
The following code is an example of a constraint, which you can set using the
Quartus II Assignment Editor:
set_location_assignment PIN_99 -to sdi_rx
set_location_assignment LC_X32_Y17_N0 -to
"sdi_megacore_top:sdi_megacore_top_inst|sdi_txrx_port:sdi_txrx_port_ge
n[0].u_txrx_port|soft_serdes_rx:rx_soft_serdes_gen.soft_serdes_rx_inst
|serdes_s2p:u_s2p|sample_a[0]"
set_location_assignment LC_X33_Y17_N0 -to
"sdi_megacore_top:sdi_megacore_top_inst|sdi_txrx_port:sdi_txrx_port_ge
n[0].u_txrx_port|soft_serdes_rx:rx_soft_serdes_gen.soft_serdes_rx_inst
|serdes_s2p:u_s2p|sample_b[0]"
set_location_assignment LC_X32_Y17_N1 -to
"sdi_megacore_top:sdi_megacore_top_inst|sdi_txrx_port:sdi_txrx_port_ge
n[0].u_txrx_port|soft_serdes_rx:rx_soft_serdes_gen.soft_serdes_rx_inst
|serdes_s2p:u_s2p|sample_c[0]"
set_location_assignment LC_X33_Y17_N1 -to
"sdi_megacore_top:sdi_megacore_top_inst|sdi_txrx_port:sdi_txrx_port_ge
n[0].u_txrx_port|soft_serdes_rx:rx_soft_serdes_gen.soft_serdes_rx_inst
|serdes_s2p:u_s2p|sample_d[0]"
Constraints for the SDI Soft Transceiver
There are constraints specific only to Cyclone devices and there are other constraints
that apply to the other devices (including Cyclone II, Cyclone III and Cyclone IV
devices). There are also different constraints that apply to the Classic timing analyzer
and the TimeQuest timing analyzer.