Altera I/O Phase-Locked Loop (Altera IOPLL) IP Core - Manual (Page 11)

Document Revision History
Date Version Changes
May 2015 2015.05.04 Updated the description for Enable access to PLL LVDS_CLK/LOADEN
output port parameter in Altera IOPLL IP Core Parameters - Settings
Tab table. Added a link to the Signal Interface Between Altera IOPLL
and Altera LVDS SERDES IP Cores table in the I/O and High Speed I/O
in Arria 10 Devices chapter.
August 2014 2014.08.18 Initial release.
UG-01155
2015.05.04
Document Revision History 11
Altera I/O Phase-Locked Loop (Altera IOPLL) IP Core User Guide Altera Corporation
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