Altera DDR SDRAM Controller - Manual (Page 46)

3–10 Chapter 3: Functional Description
Device-Level Description
DDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera Corporation
Figure 3–5. Stratix DQS Group Block Diagram (Note 1) (2)
Notes to Figure 3–5 :
(1) This figure shows the logic for one DQ output only. A complete byte group consists of eight times the DQ logic with the DQS and DM logic.
(2) All clocks are clk, unless marked otherwise.
(3) Invert combout of the IOE for the dqs pin before feeding in to inclock of the IOE for the DQ pin. This inversion is automatic if you use an
ALTDQ megafunction for the DQ pins.
(4) Optional DQS delay matching buffers controlled by the settings on the Manual Timing tab, refer to “Manual Timing Settings” on page A–1 .
(5) The optional inverters are controlled by the resynchronization edge and postamble edge settings on the Manual Timing tab, refer to “Manual
Timing Settings” on page A–1
D Q D
w rite_clk
DQS
DM
(Note 3)
d q s_oe
1
Delay
Ao
Bo
Compensated
Delay
Q
0
1
D Q
D Q
0
1
D Q
D Q
(Note 4)
Q
Q
D
D
b e
doing_ w r
d q s_ bu rst
Q D
2
Q D
Q D
Q D Q D
Q D Q D Q D
D
Q
Q Q
D Q
D
D
Q
D Q
w data
DQ
w rite_clk
doing_ w r
rdata
postam b le_clk
resynched_data
d q _ena b le
d q _capt u re_clk
resynch_clk
d q _oe
16
0
1
16
8
8
8
D
EN
EN
EN
EN
EN
doing_ w r
EN
EN
w data_valid
d q _ena b le_reset
Preset (asynchrono u s)
DQS IOEs
DM IOEs
DQ IOEs
Optional Inverter (Note 5)
Optional Inverters (Note 5)