Altera DDR SDRAM Controller - Manual (Page 93)

A–15
Examples
© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User Guide
Example A–4 shows the top-level example design file with the resynchronization
clock derived from either the write clock or the system clock.
1 The top-level design does not contain the resync_clk
.
Example A–4. Top-Level Design File (Derived Resynchronization Clock)
ddr2_top ddr2_top_ddr_sdram
(
.clk (clk),
.clk_to_sdram (unused_clk),
.clk_to_sdram_n (unused_clk_n),
.ddr2_a (ddr2_a),
.ddr2_ba (ddr2_ba),
.ddr2_cas_n (ddr2_cas_n),
.ddr2_cke (ddr2_cke),
.ddr2_cs_n (ddr2_cs_n),
.ddr2_dm (ddr2_dm[3 : 0]),
.ddr2_dq (ddr2_dq),
.ddr2_dqs (ddr2_dqs[3 : 0]),
.ddr2_odt (ddr2_odt),
.ddr2_ras_n (ddr2_ras_n),
.ddr2_we_n (ddr2_we_n),
.dqs_delay_ctrl (dqs_delay_ctrl),
.dqsupdate (dqsupdate),
.fedback_clk_out (fedback_clk_out),
.fedback_resynch_clk (fedback_resynch_clk),
.local_addr (ddr2_local_addr),
.local_be (ddr2_local_be),
.local_init_done (),
.local_rdata (ddr2_local_rdata),
.local_rdata_valid (ddr2_local_rdata_valid),
.local_rdvalid_in_n (),
.local_read_req (ddr2_local_read_req),
.local_ready (ddr2_local_ready),
.local_refresh_ack (),
.local_size (ddr2_local_size),
.local_wdata (ddr2_local_wdata),
.local_wdata_req (ddr2_local_wdata_req),
.local_write_req (ddr2_local_write_req),
.postamble_clk (dedicated_postamble_clk),
.reset_n (reset_n),
.stratix_dll_control (stratix_dll_control),
.write_clk (write_clk)
);