Zilog Z16C35 - Manual (Page 26)

ISCC
User Manual
UM011002-0808
20
the pointer bits must be set by writing to WR0 bits 2, 1, and 0 and, if required, using the
Point High command to extend the three bit pointer to registers 8 through
15. This write to WR0 to set the pointer bits may be done in either channel. There is only
one pointer register and it is used for both A and B channels. After the pointer bits are set,
the next read or write cycle to the SCC cell will access the desired register in the channel
selected during this read or write cycle. At the conclusion of this read or write cycle, the
pointer bits are reset to “0s,” so that the next access will be to WR0.
The fact that the pointer bits are reset to “0,” unless explicitly set otherwise, means that
WR0 and RR0 may also be accessed in a single cycle. That is, it is not necessary to write
the pointer bits with “0” before accessing WR0 or RR0. There are three pointer bits in
WR0, and these allow access to the registers with addresses 0 through 7. Note that a com-
mand may be written to WR0 at the same time that the pointer bits are written.
To access the registers with addresses 8 through 15, a special command must accompany
the pointer bits; WR0(4-3)=001. This precludes concurrently issuing a command when
pointing to these registers. The register map for the ISCC in the non-multiplexed bus
mode is shown in Table 2-4 below. If, for some reason, the state of the pointer bits is
unknown, they may be reset to “0” by performing a read cycle of the SCC cell. Once the
pointer bits have been set, the desired channel is selected by the state of the A1/A//B pin
during the actual read or write of the desired SCC cell register.)
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