Uart receiver operation, Receiver shift register – Zilog Z86193 User Manual
Page 125
Z8
®
CPU
User Manual
UM001604-0108
Serial Input/Output
118
The bit rate generator is started by setting the Timer Mode Register (TMR) (
F1h
) bit 1 and
bit 0 both to 1 (see
). This transfers the contents of the Prescaler 0 Register and
Counter/Timer0 Register to their corresponding down counters. In addition, counting is
enabled so that UART operations begin.
UART Receiver Operation
The receiver consists of a receiver buffer (SIO Register [
F0h
]), a serial-in, parallel-out
shift register, parity checking, and data synchronizing logic. The receiver block diagram is
displayed in
Receiver Shift Register
After a hardware reset or after a character has been received, the Receiver Shift Register is
initialized to all 1s and the shift clock is stopped. Serial data, input through Port 3 bit 0, is
synchronized to the internal clock by two D-type flip-flops before being input to the Shift
Register and the start bit detection circuitry.
The start bit detection circuitry monitors the incoming data stream, looking for a start bit
(a High-to-Low input transition). When a start bit is detected, the shift clock logic is
enabled. The T0 input is divided-by-16 and, when the count equals eight, the divider out-
puts a shift clock. This clock shifts the start bit into the Receiver Shift Register at the cen-
ter of the bit time. Before the shift actually occurs, the input is rechecked to ensure that the
start bit is valid. If the detected start bit is false, the receiver is reset and the process of
looking for a start bit is repeated. If the start bit is valid, the data is shifted into the Shift
Register every sixteen counts until a full character is assembled (see
119).
Figure 109. Timer Mode Register Bit Rate Generation
D7 D6 D5 D4 D3 D2 D1 D0
(Read/Write)
0 = No Function
1 = Load T
0
Timer Mode Register (TMR)
Register F1h
0 = Disable T
0
Count
1 = Enable T
0
Count